This version is outdated by a newer approved version.
This version (23 Oct 2018 13:03) was approved by Adrian Costina.
This version (23 Oct 2018 13:03) was approved by Adrian Costina.This is an old revision of the document!
Table of Contents
AXI_ADC_TRIGGER
The AXI_ADC_TRIGGER IP implements triggering for the ADC path and also controls two I/O triggering pins.
Features
- AXI Lite control/status interface
- Analog triggers, two channels
- Greater than a limit
- Lower than a limit
- Passing through the limit, high
- Passing through the limit, low
- Digital triggers, two trigger pins
- Low
- High
- Any edge
- Rising edge
- Falling edge
- Mixing analog and digital triggers
- Controls two IO trigger pins
Block Diagram
Interface
| Interface | Pin | Type | Description |
|---|---|---|---|
| Clock | |||
clk | input | Clock input | |
| Digital Trigger Pins | |||
trigger_i | input[1:0] | Trigger input | |
trigger_o | output[1:0] | Trigger output | |
trigger_t | output[1:0] | Trigger T signal, controlling if pin is input or output | |
| Analog Data Inputs | |||
data_a | input[15:0] | Analog data for channel A | |
data_b | input[15:0] | Analog data for channel B | |
data_valid_a | input | Data valid signal for channel A | |
data_valid_b | input | Data valid signal for channel B | |
| Analog Data Outputs | |||
data_a_trig | output[15:0] | Data with trigger embedded as most significant bit, channel A | |
data_b_trig | output[15:0] | Data with trigger embedded as most significant bit, channel B | |
data_valid_a_trig | output | Data valid for channel A | |
data_valid_b_trig | output | Data valid for channel B | |
| Fifo Depth | |||
fifo_depth | output[31:0] | Controls the dynamic depth of the history FIFO | |
| AXI_S_MM interface | |||
s_axi_* | Standard AXI Slave Memory Map interface | ||
Detailed Description
The AXI_ADC_TRIGGER IP implements triggering for the ADC path based on two trigger pins or based on the analog channel.
The trigger pins are controlled by the core and can be both input or output. For external triggering, they must be set to inputs.
The analog triggering is based on comparison with a limit. The data format must be 2's complement and maximum number of bits of the analog channel is 15. The trigger is embedded in the output word, at bit 15. Before forwarding the data to the DMA, the triggers must be extracted and data must be reconstructed. The UTIL_EXTRACT IP can be used for this purpose. Embedding the trigger with the data allows for additional IPs with unknown pipeline length to be introduced in the path.
If a history for data before the trigger is needed to be transfered, a variable FIFO IP should be used. The FIFO depth is controlled using the trigger_offset bus of this IP.
Register Map
| Address | Bits | Name | Type | Description | |
| DWORD | BYTE | ||||
| 0x0000 | 0x0000 | REG_VERSION | Version Register | ||
|---|---|---|---|---|---|
| [31:0] | VERSION | RO | Version number | ||
| 0x0001 | 0x0004 | REG_SCRATCH | Scratch Register | ||
| [31:0] | SCRATCH | RW | Scratch register | ||
| 0x0002 | 0x0008 | REG_TRIGGER_O | Control TRIGGER_O Value | ||
| [1] | TRIGGER_O[1] | RW | Set TRIGGER_O[1] value | ||
| [0] | TRIGGER_O[0] | RW | Set TRIGGER_O[0] value | ||
| 0x0003 | 0x000c | REG_IO_SELECTION | Control Trigger Pins Direction | ||
| [1] | IO_SELECTION[1] | RW | Drives the TRIGGER_T[1] pin | ||
| [0] | IO_SELECTION[0] | RW | Drives the TRIGGER_T[0] pin | ||
| 0x0004 | 0x0010 | REG_CONFIG_TRIGGER | Configure Digital Triggering | ||
| [9:8] | FALL_EDGE | RW | Enable falling edge triggering for TRIGGER[0] or TRIGGER[1] pin | ||
| [7:6] | RISE_EDGE | RW | Enable rising edge triggering for TRIGGER[0] or TRIGGER[1] pin | ||
| [5:4] | ANY_EDGE | RW | Enable any edge triggering for TRIGGER[0] or TRIGGER[1] pin | ||
| [3:2] | HIGH_LEVEL | RW | Enable high level triggering for TRIGGER[0] or TRIGGER[1] pin | ||
| [1:0] | LOW_LEVEL | RW | Enable low level triggering for TRIGGER[0] or TRIGGER[1] pin | ||
| 0x0005 | 0x0014 | REG_LIMIT_A | Analog Trigger Level for Channel A | ||
| [15:0] | LIMIT_A[15:0] | RW | Analog trigger level for channel A. 2's complement | ||
| 0x0006 | 0x0018 | REG_FUNCTION_A | Analog Triggering Function A | ||
| [1:0] | TRIGGER_FUNCTION_A | RW | Analog triggering function for channel A: 0: Lower than limit 1: higher than limit 2: pass through high limit 3: passthrough low limit |
||
| 0x0007 | 0x001c | REG_HYSTERESIS_A | Analog Trigger Histeresys for Channel A | ||
| [31:0] | HISTERESYS_A | RW | Used for the passthrough functions | ||
| 0x0008 | 0x0020 | REG_TRIGGER_MUX_A | Trigger Selection for Path A | ||
| [3:0] | TRIGGER_MUX_A | RW | Selects trigger a mode: 0: Always on 1: Digital triggering, based on trigger[0] 2: ADC triggering, based on channel A 3: Reserved 4: Digital triggering OR ADC triggering 5: Digital triggering AND ADC triggering 6: Digital triggering XOR ADC triggering 7: Option 4 negated 8: Option 5 negated 9: Option 6 negated |
||
| 0x0009 | 0x0024 | REG_LIMIT_B | Analog Trigger Level for Channel B | ||
| [15:0] | LIMIT_B[15:0] | RW | Analog trigger level for channel B. 2's complement | ||
| 0x000A | 0x0028 | REG_FUNCTION_B | Analog Triggering Function B | ||
| [1:0] | TRIGGER_FUNCTION_B | RW | Analog triggering function for channel B: 0: Lower than limit 1: higher than limit 2: pass through high limit 3: passthrough low limit |
||
| 0x000B | 0x002c | REG_HYSTERESIS_B | Analog Trigger Histeresys for Channel B | ||
| [31:0] | HISTERESYS_B | RW | Used for the passthrough functions | ||
| 0x000C | 0x0030 | REG_TRIGGER_MUX_B | Trigger Selection for Path B | ||
| [3:0] | TRIGGER_MUX_B | RW | Selects trigger B mode: 0: Always on 1: Digital triggering, based on trigger[1] 2: ADC triggering, based on channel B 3: Reserved 4: Digital triggering OR ADC triggering 5: Digital triggering AND ADC triggering 6: Digital triggering XOR ADC triggering 7: Option 4 negated 8: Option 5 negated 9: Option 6 negated |
||
| 0x000D | 0x0034 | REG_TRIGGER_MUX_OUT | Final Trigger Selection Multiplexer | ||
| [2:0] | TRIGGER_MUX_OUT | RW | Selects trigger a mode: 0: Trigger A 1: Trigger B 2: Trigger A OR Trigger B 3: Trigger A AND Trigger B 4: Trigger A XOR Trigger B |
||
| 0x000E | 0x0038 | REG_FIFO_DEPTH | Controls the Dynamic Depth of the History FIFO | ||
| [31:0] | FIFO_DEPTH | RW | Controls the depth of the history FIFO. Should be less than the maximum FIFO depth. If set to 0, the FIFO is bypassed. | ||
| 0x000F | 0x003c | REG_TRIGGERED | Indicates Triggering Status | ||
| [0] | TRIGGERED | RW1C | Indicates if the trigger has been triggered since the last time this register has been reset. | ||
| 0x0010 | 0x0040 | REG_TRIGGER_DELAY | Control the Trigger Delay | ||
| [31:0] | TRIGGER_DELAY | RW | Delays the start of data capture with TRIGGER_DELAY number of samples after the trigger. | ||
| 0x0011 | 0x0044 | REG_STREAMING | Controls Streaming Mode | ||
| [0] | STREAMING | RW | If the streaming bit is set, after the trigger condition is met data will be continuosly captured by the DMA. The streaming bit must be set to 0 to reset triggering. | ||
References
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resources/fpga/docs/axi_adc_trigger.1499094616.txt.gz · Last modified: 03 Jul 2017 17:10 by Adrian Costina