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- 2channel_cpack_1.svg
- 19 Jun 2017 11:09
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- 2channel_upack_4.svg
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- ad353xr_hdl_bd.svg
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- ad469x_hdl.svg
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- ad713x_data_interface.svg
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- ad8460_hdl.svg
- 15 Jun 2023 07:48
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- ad9083_evb_2.svg
- 09 Mar 2021 16:16
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- ad9671.svg
- 02 Mar 2017 13:50
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- ad9684.svg
- 01 Mar 2017 09:23
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- ad9695_eval_setup.jpg
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- 21 Jan 2021 10:30
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- ad9695_fmc.svg
- 07 Apr 2022 16:02
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- ad9695_fmc_8.svg
- 24 Feb 2021 09:14
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- ad9695_fmc_clocking_0.svg
- 19 Jan 2021 13:27
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- ad9695_fmc_clocking_working.svg
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- ad9695_fmc_zcu102_syncrona_setup.jpg
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- 07 Apr 2022 15:46
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- adc_crc_ad7606b_c-16.png
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- 12 Jan 2023 13:42
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- adc_datapath_01.svg
- 07 Mar 2017 10:13
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- adc_fifo_write.svg
- 19 Feb 2015 18:28
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- adc_jesd.svg
- 02 Mar 2017 11:30
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- adc_lvds_1.svg
- 09 Aug 2016 15:55
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- 12 Jan 2023 14:18
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- adc_regmap_01.svg
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- adrv9371_1.svg
- 21 Oct 2016 10:35
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- adrv9371_2.svg
- 16 Mar 2018 09:51
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- adrv9371_3.svg
- 16 Mar 2018 09:52
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- ad_dds_1.svg
- 04 Feb 2021 19:55
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- 23 Feb 2018 15:26
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- arhi_axi_ltc235x.svg
- 25 Apr 2023 10:06
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- axi_ad7606x_ip_diagr.svg
- 16 Jan 2023 20:03
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- axi_ad7616_ip.svg
- 29 Nov 2022 14:07
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- axi_ad7616_par.svg
- 30 Jun 2016 10:37
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- axi_ad7616_par_v2.svg
- 02 Aug 2016 13:43
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- axi_ad7616_ser.svg
- 30 Jun 2016 10:37
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- axi_ad7616_ser_v2.svg
- 02 Aug 2016 13:43
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- axi_ad9144.svg
- 09 Apr 2024 16:04
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- axi_ad9265.png
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- 21 Jul 2016 09:54
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- axi_ad9265_3.svg
- 09 Aug 2016 15:54
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- axi_ad9265_4.svg
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- axi_ad9361_1.svg
- 15 Nov 2016 11:34
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- axi_ad9361_2.svg
- 15 Nov 2016 11:37
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- axi_ad9361_3.svg
- 27 Jun 2017 10:00
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- axi_ad9371_2.svg
- 16 Mar 2018 09:40
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- axi_ad9467.svg
- 02 Mar 2017 10:42
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- axi_ad9467_1.svg
- 02 Mar 2017 10:43
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- axi_ad9643.svg
- 28 Feb 2017 16:11
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- axi_ad9783.jpg
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- 23 Sep 2022 16:07
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- axi_ad9783_parallel_interface.jpg
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- 10 Jan 2022 17:33
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- axi_ad9963.svg
- 15 May 2017 15:03
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- axi_adc_decimate.svg
- 24 Aug 2017 10:22
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- axi_adc_trigger.svg
- 29 May 2017 10:06
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- axi_adc_trigger_diagram.png
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- 01 Sep 2020 07:47
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- axi_clkgen.svg
- 07 Jul 2017 14:56
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- axi_clkgen_1.svg
- 07 Jul 2017 14:59
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- axi_clock_monitor.png
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- 15 Feb 2022 12:28
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- axi_dac_interpolate.svg
- 24 Aug 2017 10:24
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- axi_dmac_block_diagram.png
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- 02 Feb 2024 09:20
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- axi_dmac_block_diagram.svg
- 02 Feb 2024 09:06
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- axi_fan_control_1.svg
- 22 Mar 2019 17:23
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- axi_fan_control_pvm_vs_temp.svg
- 27 Mar 2019 10:21
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- axi_logic_analyzer.svg
- 29 May 2017 09:09
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- axi_logic_analyzer_diagram.png
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- 04 Sep 2020 12:23
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- axi_logic_analyzer_trigger.png
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- 04 Sep 2020 12:34
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- axi_ltc235x_cmos.svg
- 25 Apr 2023 08:59
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- axi_ltc235x_lvds.svg
- 25 Apr 2023 08:59
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- axi_pwm_gen.png
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- 30 Jun 2021 10:55
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- axi_pwm_gen.svg
- 07 May 2021 17:38
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- base_platform.svg
- 02 Sep 2016 17:23
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- base_platform_11.svg
- 09 Sep 2016 14:18
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- base_platform_12.svg
- 09 Sep 2016 14:20
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- cn0561_hdl_0.svg
- 11 Feb 2022 16:44
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- cn0561_hdl_1.svg
- 13 Apr 2022 10:12
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- cn0561_hdl_2.svg
- 21 Jul 2023 11:29
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- cn0561_hdl_3.svg
- 31 Jul 2023 07:28
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- cn0561_hdl_4.svg
- 31 Jul 2023 07:31
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- cn0561_hdl_5.svg
- 31 Jul 2023 07:38
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- cn0561_hdl_6.svg
- 31 Jul 2023 07:40
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- d2_phy_rec_tog.svg
- 17 Feb 2022 09:59
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- dac_datapath.svg
- 03 Nov 2017 11:05
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- dac_fifo_read.svg
- 19 Feb 2015 18:28
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- dac_jesd.svg
- 01 Mar 2017 12:12
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- dac_regmap.svg
- 10 Nov 2017 08:18
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- dds_basic.svg
- 04 Feb 2021 19:54
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- dds_clk_ratio_4.svg
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- dds_dual_tone.svg
- 04 Feb 2021 19:55
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- dds_in_dac_core.svg
- 04 Feb 2021 19:57
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- fmcomms11_bd.svg
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- fw_sync_basics.svg
- 04 Feb 2021 19:55
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- hdl_dac_interface.jpg
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- 05 Sep 2014 22:37
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- mii_recv.svg
- 21 Feb 2022 09:43
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- mii_rx.png
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- mii_transm.svg
- 21 Feb 2022 09:48
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- pcore_architecture.jpg
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- 20 Oct 2014 20:04
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- pcore_bd.jpg
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- 12 Sep 2014 18:32
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- pcore_jesd.jpg
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- 24 Nov 2014 21:31
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- phy_rec_no_toggle.png
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- phy_rec_simple.svg
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- rfifo_hdl_1.svg
- 07 Nov 2017 09:15
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- rmii_transm.svg
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- small_slave_big_master.svg
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- source_sync_if_1.svg
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- sysid1.svg
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- up_if_2.svg
- 20 Jun 2017 14:23
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- util_mii_to_rmii.drawio_3_.svg
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- xcvr_conflict.jpg
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- 08 Dec 2021 10:50
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- 08 Dec 2021 10:49
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- xcvr_rx_rearrangement.jpg
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- xcvr_tx_rearrangement.jpg
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- 08 Dec 2021 10:52
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![[root]](/resources/fpga/docs/axi_adc_decimate?ns=&tab_files=files&do=media&tab_details=view&image=resources%3Afpga%3Adocs%3Axcvr_tx_rearrangement.jpg){kind=link}
File
- Date:
- 08 Dec 2021 10:52
- Filename:
- xcvr_tx_rearrangement.jpg
- Photographer:
- Nagy, Laszlo
- Format:
- JPEG
- Size:
- 53KB
- Width:
- 822
- Height:
- 227
- References for:
- UTIL_ADXCVR core for Xilinx devices
resources/fpga/docs/axi_adc_decimate.txt · Last modified: 14 Dec 2023 17:02 by Andrei Grozav