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resources:fpga:docs:axi_adc_decimate [06 Jun 2018 12:52] – Reviewed Adrian Costinaresources:fpga:docs:axi_adc_decimate [31 Aug 2020 15:06] – Add data delay signals Andrei Grozav
Line 36: Line 36:
 |              | ''adc_dec_valid_a'' | ''output'' | Data valid for channel A | |              | ''adc_dec_valid_a'' | ''output'' | Data valid for channel A |
 |              | ''adc_dec_valid_b'' | ''output'' | Data valid for channel B | |              | ''adc_dec_valid_b'' | ''output'' | Data valid for channel B |
 +|              | ''adc_data_rate'' | ''output[2:0]'' | Data rate (decimation ratio) |
 +|              | ''adc_oversampling_en'' | ''output'' | Data oversampling enabled |
 | **AXI_S_MM interface** |||| | **AXI_S_MM interface** ||||
 |              | ''s_axi_*'' || Standard AXI Slave Memory Map interface | |              | ''s_axi_*'' || Standard AXI Slave Memory Map interface |
resources/fpga/docs/axi_adc_decimate.txt · Last modified: 14 Dec 2023 17:02 by Andrei Grozav

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