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resources:fpga:docs:axi_ad9671 [13 Oct 2021 09:48] – Edit footer & add reference to generic ADC Iulia Moldovanresources:fpga:docs:axi_ad9671 [25 Apr 2023 09:42] (current) – Edit according to template Iulia Moldovan
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-====== AXI_AD9671 IP core ======+====== AXI_AD9671 ====== 
 + 
 +===== Overview =====
  
 The [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_ad9671|axi_ad9671]] IP core can be used to interface the [[adi>AD9671]] Octal Ultrasound AFE with digital demodulator. The [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_ad9671|axi_ad9671]] IP core can be used to interface the [[adi>AD9671]] Octal Ultrasound AFE with digital demodulator.
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-===== Block Diagram =====+===== Block diagram =====
  
 {{  :resources:fpga:docs:adc_jesd.svg | AXI_AD9671 Block diagram }} {{  :resources:fpga:docs:adc_jesd.svg | AXI_AD9671 Block diagram }}
  
  
-===== Configuration Parameter =====+===== Configuration parameters =====
  
 ^ Name ^ Description ^ Default Value^ ^ Name ^ Description ^ Default Value^
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-===== Detailed Architecture =====+===== Architecture =====
  
 {{  :resources:fpga:docs:ad9671.svg | AXI_AD9671 IP architecture?800x600}} {{  :resources:fpga:docs:ad9671.svg | AXI_AD9671 IP architecture?800x600}}
 \\ \\
  
-===== Detailed Description =====+===== Description =====
  
 The top module, axi_ad9671, instantiates: \\ The top module, axi_ad9671, instantiates: \\
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-===== Register Map =====+===== Design Guidelines =====
  
-{{page>:resources:fpga:docs:hdl:regmap##Base (common to all cores)&nofooter&noeditbtn}}+The control of the AD9671 chip is done through a SPI interface, which is needed at system level.
  
-{{page>:resources:fpga:docs:hdl:regmap##ADC Common (axi_ad*)&nofooter&noeditbtn}}+The design should use a DMA to move the data from the output of the IP to memory.
  
-{{page>:resources:fpga:docs:hdl:regmap##ADC Channel (axi_ad*)&nofooter&noeditbtn}}+If the data needs to be processed in HDL before moved to the memory, it can be done at the output of the IP (at system level) or inside of the adc channel module (at IP level).
  
  
-===== Design Guidelines =====+===== Register map =====
  
-The control of the AD9671 chip is done through a SPI interface, which is needed at system level.+{{page>:resources:fpga:docs:hdl:regmap##Base (common to all cores)&nofooter&noeditbtn}}
  
-The design should use a DMA to move the data from the output of the IP to memory.+{{page>:resources:fpga:docs:hdl:regmap##ADC Common (axi_ad*)&nofooter&noeditbtn}}
  
-If the data needs to be processed in HDL before moved to the memory, it can be done at the output of the IP (at system level) or inside of the adc channel module (at IP level).+{{page>:resources:fpga:docs:hdl:regmap##ADC Channel (axi_ad*)&nofooter&noeditbtn}}
  
  
resources/fpga/docs/axi_ad9671.txt · Last modified: 25 Apr 2023 09:42 by Iulia Moldovan

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