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AXI_AD7616 IP core

The axi_ad7616 IP core can be used to interface the AD7616 device using an FPGA. The core has a AXI Memory Map interface for configuration, supports the parallel data interface of the device, and has a simple FIFO interface for the DMAC.

More about the generic framework interfacing ADCs can be read here: axi_adc_ip.

AXI_AD7616 with Parallel Interface

AXI_AD7616 with Parallel Interface

Configuration Parameter

Name Description Default Value
ID Core ID, it can be used in case of multiple cores on a system 0

Signal and Interface Pins

Interface Pin Type Description
rx_parallel Parallel interface
rx_db_o output[15:0] Parallel data out
rx_db_i input[15:0] Parallel data in
rx_db_t output active High 3-state T pin for IOBUF
rx_rd_n output Active low parallel data read control
rx_wr_n output Active low parallel data write control
rx_cs_n output Active low chip select
rx_control Control interface
rx_trigger input End of conversion signal
s_axi_* AXI Slave Memory Map interface
adc_fifo Write FIFO interface for the DMAC
adc_valid output Shows when a valid data is available on the bus
adc_data output[15:0] Data bus
adc_sync output Shows the first valid beat on a sequence
irq IRQ signal

Memory Map Registers

Address Bits Name Type Description
0x0100 0x0400 REG_VERSION Version and Scratch Registers
[31:0] VERSION[31:0] RO Version number.
0x0101 0x0404 REG_ID Version and Scratch Registers
[31:0] ID[31:0] RO Instance identifier number.
0x0102 0x0408 REG_SCRATCH Version and Scratch Registers
[31:0] SCRATCH[31:0] RW Scratch register.
0x0110 0x0440 REG_UP_CNTRL ADC Interface Control & Status
[0] RESETN RW Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
[1] CNVST_EN RW Enable the CNVST pulse generator of core.
0x0111 0x0444 REG_UP_CONV_RATE ADC Interface Control & Status
[31:0] UP_CONV_RATE RW Rate of the conversion pulse signal, it's relative to the system clock (s_axis_clk).
0x0112 0x0448 REG_UP_BURST_LENGTH ADC Interface Control & Status
[4:0] UP_BURST_LENGTH RW Define the actual burst length. The value must be equal to burst length - 1 . This register is active just on PARALLEL mode.
0x0113 0x044C REG_UP_READ_DATA ADC Interface Control & Status
[31:0] UP_READ_DATA RO This register can be used to read the device registers on PARALLEL software mode.
0x0114 0x0450 REG_UP_WRITE_DATA ADC Interface Control & Status
[31:0] UP_WRITE_DATA WO This register can be used to write the device registers on PARALLEL software mode.

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resources/fpga/docs/axi_ad7616.1670928307.txt.gz · Last modified: 13 Dec 2022 11:45 by sergiu arpadi