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--- resources:eval:user-guides:pzsdr:power-and-sequencing [24 Aug 2016 18:22] – [Software Settings - Input Voltage Range Determination and Setting] Neil Wilson
+++ resources:eval:user-guides:pzsdr:power-and-sequencing [03 Jan 2021 21:46] (current) – fix links Robin Getz
@@ Line 130: / Line 130: @@
   * 1 PZSDR Board.
   * 1 microSD card (with appropriate image).
-  * 1 [[http://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval_usb-sdp-cablez.html#eb-overview|USB-SDP-CABLEZ Serial I/O Interface]] cable
+  * 1 [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval_usb-sdp-cablez.html#eb-overview|USB-SDP-CABLEZ Serial I/O Interface]] cable
   {{ :resources:eval:user-guides:pzsdr:usb-sdp-cablez.png?600 }}
   * 1 Custom Adapter for the USB-SDP-CABLEZ.
   {{ :resources:eval:user-guides:pzsdr:adapter_board_t_b.jpg?200 }}
-  * [[http://www.analog.com/en/products/power-management/sequencing/digital-sequencers/adm1166.html#product-requirement|ADMxxxx Run Time Installer]].
+  * [[adi>en/products/power-management/sequencing/digital-sequencers/adm1166.html#product-requirement|ADMxxxx Run Time Installer]].
-  * [[http://www.analog.com/en/products/power-management/sequencing/digital-sequencers/adm1166.html#product-requirement|Super Sequencer Configuration Tool]].
+  * [[adi>en/products/power-management/sequencing/digital-sequencers/adm1166.html#product-requirement|Super Sequencer Configuration Tool]].
 ===Software Setup===
@@ Line 178: / Line 178: @@
   - Disconnect the custom adapter from the PZSDR board.
-====Software Settings - Input Voltage Range Determination and Setting====
+===Something went wrong... what can I do?===
+In the event you are staring at a PCB with no power, don't panic, there are options!
+The easiest thing to do is to plug in your USB-SDP-CABLEZ, as detailed in the instructions above.  Navigate to the 'Readback' tab.  From here you can observe each of the VH, VPx, VXx input voltages as read by the ADM1166.
+{{:resources:eval:user-guides:pzsdr:power-and-sqeuencing:adm1166_readback.png?600|}}
+=====Software - Input Voltage Range Determination and Setting=====
 The following provides a detailed overview on how the ADM1166 input voltage ranges are calculated and programmed to account for input and output ZYNQ voltage settings, ADM116 power sequencer input voltage ranges etc.
-=== ZYNQ I/O Voltage Range ===
+====ZYNQ I/O Voltage Range====
 Starting with the XC7Z035 ZYNQ [[http://xilinx.com/support/documentation/data_sheets/ds191-XC7Z030-XC7Z045-data-sheet.pdf | Zynq-7000 All Programmable SoC: DC and AC Switching Characteristics]] we see the following I/O voltage ranges for the banks of the ZYNQ.
@@ Line 194: / Line 201: @@
-=== ADM1166 Super Sequencer Input Voltage Ranges ===
+====ADM1166 Super Sequencer Input Voltage Ranges ====
 The ADM1166 has several input voltage ranges for the VP pins and VX pins.  The VX pins only work on the Ultra-Low Range setting.
@@ Line 206: / Line 213: @@
-=== The Problem! ===
+====The Problem! ====
 Unfortunately the VCCO I/O voltage levels don’t fit inside any one range of the sequencer.  1.14V is below the minimum voltage of the Low-Range (1.25V), and the 1.89V/3.465V is above the maximum voltage of the Ultra-Low Range (1.375V).
-=== Fixing the problem for HP Banks 33 and 34 ===
+==== Fixing the problem for HP Banks 33 and 34 ====
-A resistor divider is added between the bank voltage and the ADM1166 input.
+A resistor divider is added between the bank voltage and the ADM1166 input. The input impedance of the IC to ground (R3) is in parallel with R2.
+{{:resources:eval:user-guides:pzsdr:power-and-sqeuencing:adm1166_input_impedance.png?600|}}
-The input impedance of the IC to ground (R3) has a minimum value of 26k and maximum value of 104k.  This resistor  is in parallel with R2.
+Its resistance varies from 20k to 60k depending on the input voltage to the device.  The information below is for a single part, not including temperature, supply or any other variation.
-Calculating the min and max value of this parallel resistance gives...
+{{:resources:eval:user-guides:pzsdr:power-and-sqeuencing:adm1166_input_impedance_graph.png?400|}}
+The resistor divider was designed so the worst case output voltage fits inside the Ultra-Low Range.
+Some iteration and simulation was done to determine the input impedance of the device for each particular voltage setting.
+  * When JX_VCCO_33_34 = 1.14V, the input impedance of the IC is 35k.
+  * When JX_VCCO_33_34 = 1.89V, the input impedance of the IC is 23k.
+Calculating the parallel impedance of R2 and R3.
 ^ Description      ^ Ohms       ^ Ohms       ^
 | R2        | 10.0k  | 10.0k |
-| R3        | 26k    | 104k  |
+| R3        | 35k    | 23k  |
-| R2 P R3   | 7.22k  | 9.12k |
+| R2 P R3   | 7.777k  | 6.96k |
-The resistor divider was designed so the worst case output voltage fits inside the Ultra-Low Range.
 Revisiting good old’ Ohm’s law gives:
-  * JX_VCCO_33_34_SEQ = (1.14V * 7220) / (4020+7120) = 0.732V
+  * JX_VCCO_33_34_SEQ = (1.14V * 7777) / (4020+7777) = 0.7515V
-  * JX_VCCO_33_34_SEQ = (1.89V * 9120) / (4020+9120) = 1.311V
+  * JX_VCCO_33_34_SEQ = (1.89V * 6969) / (4020+6969) = 1.198V
 Both of these values are inside the Ultra-Low Range input voltage setting of the power sequencer.
+==== Fixing the problem for HR Banks 12 and 13 ====
+Now to look at the resistor dividers for bank 12 (HR bank).  Bank 13 is also an HR bank with the same resistor divider so the calculations are identical for it, and will not be replicated.  The resistor divider was designed so the output voltage fits inside the Mid-Range, kind of.  The resistor values are swapped and the bottom leg of the divider is connected to a 3.3V supply found on the PCB.
+{{:resources:eval:user-guides:pzsdr:power-and-sqeuencing:bank_12_and_13_resistor_divider.png?400|}}
+Now for some nodal analysis!
+  * I(R1) = (VOUT - V1)/(R1)
+  * I(R2) = (V2 - VOUT)/(R2)
+  * I(R3) = (VOUT)/(R3)
+    * I(R2) - I(R1) = I(R3)
+      * (V2-VOUT)/(R2) - (VOUT-V1)/(R1) = [(VOUT)/(R3)]
+        * Multiply everything by R1*R2*R3.
+      * (V2*R1*R3) - (VOUT*R1*R3) - (VOUT*R2*R3) + (V1*R2*R3) = (VOUT*R1*R2)
+        * Collect all Vout terms on the same side.
+      * (VOUT*R1*R2) + (VOUT*R2*R3) + (VOUT*R1*R3) = (V2*R1*R3) + (V1*R2*R3)
+      * VOUT*[(R1*R2) + (R2*R3) + (R1*R3)] = (V2*R1*R3) + (V1*R2*R3)
+      * VOUT = [(V2*R1*R3) + (V1*R2*R3)] / [(R1*R2) + (R2*R3) + (R1*R3)]
-=== Fixing the problem for HR Banks 12 and 13 ===
+Now, just fill in the variables.
-Now to look at the resistor dividers for bank 12 (HR bank).  Bank 13 is also an HR bank with the same resistor divider so the calculations are identical.  The resistor divider was designed so the output voltage fits inside the Mid-Range.  The resistor values are swapped and the bottom leg of the divider is connected to a 3.3V supply found on the PCB.
+For the smallest possible ZYNQ output voltage and smallest possible ADM1166 input impedance.
+      * VOUT = [(V2*R1*R3) + (V1*R2*R3)] / [(R1*R2) + (R2*R3) + (R1*R3)]
+      * VOUT = 2.431V
-Now for some nodal analysis!
+The input impedance of the IC is found from the same graph as above.
-  * JX_VCCO_12_SEQ = (3V3_I2C)-(I*R2)
-  * JX_VCCO_12_SEQ = (3V3_I2C)-(((∆V) / (R1+R2))*R2)
-  * JX_VCCO_12_SEQ = (3V3_I2C)-((((3V3_I2C)–(JX_VCCO_12))/(R1+R2))xR2))
-  * JX_VCCO_12_SEQ = (3.3)-(((3.3-1.14)/(14020))*4020) = 2.680V
-This shows the lowest possible output voltage of the ZYNQ, sits above the 2.5V minimum value of the Mid-Range.  Now to verify the largest possible output voltage of the ZYNQ, 3.465V.  The current will flow the other way because of physics.
+{{:resources:eval:user-guides:pzsdr:power-and-sqeuencing:adm1166_input_impedance_graph.png?400|}}
+This shows the smallest possible output voltage of the ZYNQ does NOT sit in the Mid-Range setting.  So the minimum input for this range is 2.5V.  This will accommodate most use cases.
+-------------------------------------
+If you are trying to use 1.2V for the HR bank 12 or bank 13, YOU MUST CHANGE to the low range setting.
-  * JX_VCCO_12_SEQ = (3V3_I2C) + (I x R2)
+Repeat....
-  * JX_VCCO_12_SEQ = (3V3_I2C) +  ((∆V / (R1 + R2)) * R2)
-  * JX_VCCO_12_SEQ = (3V3_I2C) + (((JX_VCCO_12 – 3V3_I2C) / (R1 + R2)) * R2))
-  * JX_VCCO_12_SEQ = 3.3 + (((3.465-3.3) / (14020)) * 4020)) = 3.347V
-This verifies the largest ZYNQ output voltage for the HR banks sits inside the Mid-Range.
+If you are trying to use 1.2V for the HR bank 12 or bank 13, YOU MUST CHANGE to the low range setting.
+-------------------------------------
+For the largest possible ZYNQ output voltage and largest possible ADM1166 input impedance.
+      * VOUT = [(V2*R1*R3) + (V1*R2*R3)] / [(R1*R2) + (R2*R3) + (R1*R3)]
+      * VOUT = 3.041V
+This shows the largest ZYNQ output voltage for the HR banks sits inside the Mid-Range, after going through the resistor divider.
-=== Resistor Tolerance Consideration ===
-A final consideration is to include the 1% resistor tolerance in calculations.  This insures the worst case drift will not cause a voltage to be above or below threshold.
-In the case where JX_VCCO_12 = 1.14V, the minimum output voltage exists in the situation where R1 is 1% low (9900 Ohms) and R2 is 1% high (4060.2 Ohms).    Re-calculating the equation from above gives JX_VCCO_12_SEQ = 2.671V.
- In the case where JX_VCCO_12 = 3.465V, the maximum output voltage exists in the situation where R1 is 1% low (9900 Ohms) and R2 is 1% high (4060.2 Ohms).  Re-calculating the equation from above gives JX_VCCO_12_SEQ = 3.348V.
-=== So what does it all mean? ===
+==== So what does it all mean? ====
 This table summarizes the final results including 1% resistor tolerance.  The MGTAVCC and MGTAVTT already fit into the ultralow range of the sequencer.  In order for the HR and HP banks to fit inside the ADM1166 input range, a resistor divider must be used to divide down the VCCO_12, VCCO_13 and VCCO_33_34 voltages.
@@ Line 275: / Line 303: @@
 | VMGTAVCC        | Ultralow | 0.970 V | 1.080 V |  X      |  X      | 0.573 V | 1.375 V |
 | VMGTAVTT        | Ultralow | 1.170 V | 1.230 V |  X      |  X      | 0.573 V | 1.375 V |
-| VCCO (HR Bank)  | Mid-Range| 1.140 V | 3.465 V | 2.671 V | 3.348 V | 2.500 V | 6.000 V |
+| VCCO (HR Bank)  | Mid-Range| 1.140 V | 3.465 V | 2.431 V | 3.043 V | 2.500 V | 6.000 V |
-| VCCO (HP Bank)  | Ultralow | 1.140 V | 1.890 V | 0.808 V | 1.356 V | 0.573 V | 1.375 V |
+| VCCO (HP Bank)  | Ultralow | 1.140 V | 1.890 V | 0.748 V | 1.192 V | 0.573 V | 1.375 V |
-=== Resistor divider values ===
+==== Resistor divider values ====
 The table below summarizes the resistor values used in the PicoZed SDR SOM 2 design.
 All resistors are 1%.
@@ Line 299: / Line 327: @@
-=== So… how do I setup the sequencer? ===
+==== So… how do I setup the sequencer? ====
 No worries… when a user purchases the PicoZed SDR 2x2 SOM, the sequencer comes pre-programmed with all of this information!
 If so inclined, you can change these settings by opening the software and utilizing the USB-SDP-CABLEZ dongle available for purchase from the ADI website.
@@ Line 314: / Line 342: @@
 JX_VCCO_12
-{{:resources:eval:user-guides:pzsdr:power-and-sqeuencing:vcco_12_software.png?600|}}
+{{:resources:eval:user-guides:pzsdr:power-and-sqeuencing:sw_jx_vcco_12.png?600|}}
 JX_VCCO_13
-{{:resources:eval:user-guides:pzsdr:power-and-sqeuencing:vcco_13_software.png?600|}}
+{{:resources:eval:user-guides:pzsdr:power-and-sqeuencing:sw_jx_vcco_13.png?600|}}
 JX_VCCO_33_34
@@ Line 327: / Line 355: @@
 The ADM1166 Super Sequencer Software shows where to select the range for each input pin (VP or VX), how to set the desired UV/OV thresholds, hysteresis on these thresholds, what fault type to look for and a glitch delay.
-=== But wait… the calculated tables are slightly different from the software values! ===
+==== But wait… the calculated tables are slightly different from the software values! ====
-The thresholds are programmed using 8-bit resolution so the program was written to be as close to the UV or OV threshold, without restricting the range at all.
+The thresholds are programmed using 8-bit resolution so the program was written to be as close to the UV or OV threshold, without restricting the range, and in some cases adding a small amount of headroom.
+==== This looks great, but, I need to change some settings for my custom carrier. ====
+Thinking of modifying the VH Thresholds? Then think again... no, seriously... think about what you want to do.  Be very careful! These thresholds are designed based on the FMC Carrier to account for absolute worst case diode voltage drop over current and temperature.
+{{:resources:eval:user-guides:pzsdr:power-and-sqeuencing:sw_vh.png?400|}}
-=== This looks great, but, I need to change some settings for my custom carrier. ===
-Thinking of modifying the VH Thresholds? Be very careful! They are designed based on the FMC Carrier to account for diode voltage drop over current and temperature.
 Thinking of modifying other settings? Still be careful!
-This is not to say DON’T change settings, merely… think twice, then think twice more, then program once.
+This is not to say DON’T change settings, merely… think twice, then think twice more, then program once.  The worst thing to happen is to have a board with no power and no way to reprogram the threshold you just changed.
-=== I programmed twice and thought once.===
+==== I programmed twice and thought once.====
 Did you adjust a setting incorrectly?  Now the sequencer won’t allow the system to boot up because you typed the under voltage threshold into the over voltage threshold field?
 This is not a problem.  If you have the USB-SDP-CABLEZ dongle, go here, do some more reading and you will be back up and running in no time.
@@ Line 341: / Line 376: @@
 The link provided gives significant detail on how to program the sequencer using the dongle or through a linux script.
-=== Is there a default file I can load? ===
+==== Is there a default file I can load? ====
 The default file that comes pre-loaded when you order hardware can be found on [[https://github.com/analogdevicesinc/PicoZed-SDR| Github]].
+This file is also updated on occasion to include new features, tweaks or other items which pop up as systems are developed.
 {{navigation PicoZed_SDR#none#resources/eval/user-guides/picozed_sdr|PicoZed_SDR#none#}}

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