Sequence and timing information for the PicoZed SDR is controlled by the ADM1166 Super Sequencer with Margining Control and Nonvolatile Fault Recording. These files and information were designed in accordance with Xilinx product specification Zynq-7000 All Programmable SoC: DC and AC Switching Characteristics to prevent damage to the FPGA.
The diagram below details the timing and order of operation for every enable pin, voltage rail, gated transistor and sequencer state on the board. This information is meant to be used in conjunction with the state diagram, Xilinx document and sequencer code to provide a more complete understanding of this complicated power design.
Some of the voltages for this design are generated by the Avnet PicoZed SDR Carrier Card and brought to the PicoZed SDR through connectors JX1 - JX4. These voltages are gated by a transistor and must be qualified by the sequencer before they can pass to other components on the board. The remainder of the voltages are generated on board by and LDO or switcher.
The sequencer qualifies a particular voltage then drives the enable pin high to turn on the next voltage for qualification and/or to drive a transistor gate and allow that particular voltage access to the downstream circuitry.
For example, in state 3 of the sequencing engine, the ADM1166 will check if the '1.0V' is in range. If yes, the state machine will attempt to turn on '1.8V' by setting '1.8V_EN' high. If no, the state machine will take appropriate action. State 4 checks the '1.8V' rail is in range, and tries to enable '1.35V' by setting '1.35V_EN' high. So on and so forth.
The timing diagram can be downloaded here. The tool used to generate this diagram isTiming Diagram Editor
The state diagram is available in pdf format sequencer_state_diagram.pdf.
In the command line of your favorite terminal program, enter the following:
root@analog:~#git clone https://github.com/analogdevicesinc/PicoZed-sdr.git Cloning into 'PicoZed-sdr'... remote: Counting objects: 13, done. remote: Compressing objects: 100% (11/11), done. remote: Total 13 (delta 2), reused 0 (delta 0), pack-reused 0 Unpacking objects: 100% (13/13), done. Checking connectivity... done. root@analog:~# cd PicoZed-sdr/ root@analog:~# cd SDR2_ADM1166_updates/ root@analog:~# chmod +x ./adm1166_eeprom root@analog:~# ./adm1166_eeprom ADM1166.hex Starting to reprogramm the AD1166 EEPROM. Reading f800 ... success ... existing memory is identical. Reading f820 ... success ... existing memory is identical. Reading f840 ... success ... existing memory is identical. Reading f860 ... success ... existing memory is identical. Reading f880 ... success ... existing memory is identical. Skipping reserved page f8a0 Skipping reserved page f8c0 Skipping reserved page f8e0 Reading f900 ... success ... existing memory is identical. Reading f920 ... success ... existing memory is identical. Reading f940 ... success ... existing memory is identical. Reading f960 ... success ... existing memory is identical. Reading f980 ... success ... existing memory is identical. Skipping reserved page f9a0 Skipping reserved page f9c0 Skipping reserved page f9e0 Reading fa00 ... success ... existing memory is identical. Reading fa20 ... success ... existing memory is identical. Reading fa40 ... success ... existing memory is identical. Reading fa60 ... success ... existing memory is identical. Reading fa80 ... success ... existing memory is identical. Skipping reserved page faa0 Skipping reserved page fac0 Skipping reserved page fae0 Reading fb00 ... success ... existing memory is identical. Reading fb20 ... success ... existing memory is identical. Reading fb40 ... success ... existing memory is identical. Reading fb60 ... success ... existing memory is identical. Reading fb80 ... success ... existing memory is identical. Skipping reserved page fba0 Skipping reserved page fbc0 Skipping reserved page fbe0 Successfully reprogrammed the ADM1166 EEPROM. ... reboot the board to load the new configuration. root@analog:~#
Reboot the board and the new EEPROM configuration will be implemented.
In the event you are staring at a PCB with no power, don't panic, there are options! The easiest thing to do is to plug in your USB-SDP-CABLEZ, as detailed in the instructions above. Navigate to the 'Readback' tab. From here you can observe each of the VH, VPx, VXx input voltages as read by the ADM1166.
The following provides a detailed overview on how the ADM1166 input voltage ranges are calculated and programmed to account for input and output ZYNQ voltage settings, ADM116 power sequencer input voltage ranges etc.
Starting with the XC7Z035 ZYNQ Zynq-7000 All Programmable SoC: DC and AC Switching Characteristics we see the following I/O voltage ranges for the banks of the ZYNQ.
|VMGTAVCC||0.97 V||1.080 V|
|VMGTAVTT||1.17 V||1.230 V|
|VCCO (HR Bank)||1.14 V||3.465 V|
|VCCO (HP Bank)||1.14 V||1.890 V|
The ADM1166 has several input voltage ranges for the VP pins and VX pins. The VX pins only work on the Ultra-Low Range setting.
|Mid-Range||2.5000 V||6.000 V||X||X|
|Low Range||1.250 V||3.000 V||X||X|
|Ultra-Low Range||0.573 V||1.375 V||0.573 V||1.375 V|
VMGTAVCC and VMGTAVTT drive directly into the VX3 and VX4 pins of the ADM1166. The I/O voltage range lines up nicely inside input voltage range of the sequencer. 1.14V is above the minimum voltage of the Ultra-Low Range (0.573V) and 1.23V is below the maximum voltage of the Ultra-Low Range (1.375V).
Unfortunately the VCCO I/O voltage levels don’t fit inside any one range of the sequencer. 1.14V is below the minimum voltage of the Low-Range (1.25V), and the 1.89V/3.465V is above the maximum voltage of the Ultra-Low Range (1.375V).
A resistor divider is added between the bank voltage and the ADM1166 input. The input impedance of the IC to ground (R3) is in parallel with R2.
Its resistance varies from 20k to 60k depending on the input voltage to the device. The information below is for a single part, not including temperature, supply or any other variation.
The resistor divider was designed so the worst case output voltage fits inside the Ultra-Low Range. Some iteration and simulation was done to determine the input impedance of the device for each particular voltage setting.
Calculating the parallel impedance of R2 and R3.
|R2 P R3||7.777k||6.96k|
Revisiting good old’ Ohm’s law gives:
Both of these values are inside the Ultra-Low Range input voltage setting of the power sequencer.
Now to look at the resistor dividers for bank 12 (HR bank). Bank 13 is also an HR bank with the same resistor divider so the calculations are identical for it, and will not be replicated. The resistor divider was designed so the output voltage fits inside the Mid-Range, kind of. The resistor values are swapped and the bottom leg of the divider is connected to a 3.3V supply found on the PCB.
Now for some nodal analysis!
Now, just fill in the variables.
For the smallest possible ZYNQ output voltage and smallest possible ADM1166 input impedance.
The input impedance of the IC is found from the same graph as above.
This shows the smallest possible output voltage of the ZYNQ does NOT sit in the Mid-Range setting. So the minimum input for this range is 2.5V. This will accommodate most use cases.
If you are trying to use 1.2V for the HR bank 12 or bank 13, YOU MUST CHANGE to the low range setting.
If you are trying to use 1.2V for the HR bank 12 or bank 13, YOU MUST CHANGE to the low range setting.
For the largest possible ZYNQ output voltage and largest possible ADM1166 input impedance.
This shows the largest ZYNQ output voltage for the HR banks sits inside the Mid-Range, after going through the resistor divider.
This table summarizes the final results including 1% resistor tolerance. The MGTAVCC and MGTAVTT already fit into the ultralow range of the sequencer. In order for the HR and HP banks to fit inside the ADM1166 input range, a resistor divider must be used to divide down the VCCO_12, VCCO_13 and VCCO_33_34 voltages.
|Zynq Voltage Rail||ADM1166 Range||Datasheet Min||Datasheet Max||Divider Vout Min||Divider Vout Max||ADM1166 Input Min||ADM1166 Input Max|
|VMGTAVCC||Ultralow||0.970 V||1.080 V||X||X||0.573 V||1.375 V|
|VMGTAVTT||Ultralow||1.170 V||1.230 V||X||X||0.573 V||1.375 V|
|VCCO (HR Bank)||Mid-Range||1.140 V||3.465 V||2.431 V||3.043 V||2.500 V||6.000 V|
|VCCO (HP Bank)||Ultralow||1.140 V||1.890 V||0.748 V||1.192 V||0.573 V||1.375 V|
The table below summarizes the resistor values used in the PicoZed SDR SOM 2 design. All resistors are 1%.
|VCCO (HR Bank)||Ultralow||1.140 V||10.0k||4.02k||3.300 V|
|VCCO (HR Bank)||Ultralow||3.465 V||10.0k||4.02k||3.300 V|
|VCCO (HP Bank)||Mid-Range||1.140 V||4.02k||10.0k||0.000 V|
|VCCO (HP Bank)||Ultralow||1.890 V||4.02k||10.0k||0.000 V|
No worries… when a user purchases the PicoZed SDR 2×2 SOM, the sequencer comes pre-programmed with all of this information! If so inclined, you can change these settings by opening the software and utilizing the USB-SDP-CABLEZ dongle available for purchase from the ADI website. The pictures below show the default states for the voltage rails discussed in this adventure!
The ADM1166 Super Sequencer Software shows where to select the range for each input pin (VP or VX), how to set the desired UV/OV thresholds, hysteresis on these thresholds, what fault type to look for and a glitch delay.
The thresholds are programmed using 8-bit resolution so the program was written to be as close to the UV or OV threshold, without restricting the range, and in some cases adding a small amount of headroom.
Thinking of modifying the VH Thresholds? Then think again… no, seriously… think about what you want to do. Be very careful! These thresholds are designed based on the FMC Carrier to account for absolute worst case diode voltage drop over current and temperature.
Thinking of modifying other settings? Still be careful! This is not to say DON’T change settings, merely… think twice, then think twice more, then program once. The worst thing to happen is to have a board with no power and no way to reprogram the threshold you just changed.
Did you adjust a setting incorrectly? Now the sequencer won’t allow the system to boot up because you typed the under voltage threshold into the over voltage threshold field? This is not a problem. If you have the USB-SDP-CABLEZ dongle, go here, do some more reading and you will be back up and running in no time. If you DON’T have a USB-SDP-CABLEZ dongle… you modified the sequencer software through some other means … take a deep breath… relax… then order a USB-SDP-CABLEZ dongle, go here, do some more reading and you will be back up and running in no time. The link provided gives significant detail on how to program the sequencer using the dongle or through a linux script.
The default file that comes pre-loaded when you order hardware can be found on Github.
This file is also updated on occasion to include new features, tweaks or other items which pop up as systems are developed.