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| resources:eval:user-guides:high-temp:ev-ht-200cdaq1:hardware [01 Mar 2018 03:29] – updated product page links Jeff Watson | resources:eval:user-guides:high-temp:ev-ht-200cdaq1:hardware [08 Jan 2021 09:52] (current) – Fixed bad link for EV-HT-200CDAQ1 Ioana Chelaru |
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| ====== EV-HT-200CDAQ1 Hardware Design Notes ====== | ====== EV-HT-200CDAQ1 Hardware Design Notes ====== |
| [[http://www.analog.com/ev-ht-200cdaq1|EV-HT-200CDAQ1]] builds on the [[http://www.analog.com/CN0365|CN0365]] analog front end reference design with the goal of providing a foundation for a high temperature, low power microcontroller-based data acquisition and control solution that meets the requirements for many downhole instrumentation and other high temperature applications. Based upon the AD7981 analog-to-digital SAR converter, this reference design demonstrates a full featured system with two high speed simultaneously sampled channels along with 8 additional multiplexed channels suitable for covering the acquisition requirements of a broad range of downhole tools (10 channels total). This analog front end is connected via SPI ports to the VA10800 ARM® Cortex®-M0 microcontroller from VORAGO Technologies, an Analog Devices Alliance Partner. | [[adi>en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EV-HT-200CDAQ1.html|EV-HT-200CDAQ1]] builds on the [[adi>CN0365|CN0365]] analog front end reference design with the goal of providing a foundation for a high temperature, low power microcontroller-based data acquisition and control solution that meets the requirements for many downhole instrumentation and other high temperature applications. Based upon the AD7981 analog-to-digital SAR converter, this reference design demonstrates a full featured system with two high speed simultaneously sampled channels along with 8 additional multiplexed channels suitable for covering the acquisition requirements of a broad range of downhole tools (10 channels total). This analog front end is connected via SPI ports to the VA10800 ARM® Cortex®-M0 microcontroller from VORAGO Technologies, an Analog Devices Alliance Partner. |
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| {{ :resources:eval:user-guides:high-temp:ev-ht-200cdaq1:block_diagram.jpg?direct |}} | {{ :resources:eval:user-guides:high-temp:ev-ht-200cdaq1:block_diagram.jpg?direct |}} |
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| ===== Analog Input Channel ===== | ===== Analog Input Channel ===== |
| The design of the data acquisition channel for the EV-HT-200CDAQ1 is covered extensively by the[[http://www.analog.com/CN0365|CN0365]] application note. That design serves as the basis for the three ADC inputs on this platform, although some changes and optimizations were made, mostly in passive component selection, in order to address the form factor requirements of the board and extended reliable operation up to 200°C. The reference acquisition channel circuit is shown the schematic below. There are two “digital multiplexed” channels that each contain a complete data acquisition channel, similar to CN0365, that are capable of running at high sample rates. There is also an “analog multiplexed” channel that adds an ADG798 multiplexer in front of the inputs, optimized for lower throughput inputs. R1 and R3 provide a 1.25 V bias for the non-inverting input of U1, and prevent it from floating to the rail of the analog input if left open, or if the multiplexer is de-selected. R8 and R9 can be changed to increase the gain of U1. R4, R7, and C1 are the anti-aliasing filter, but they can be re-configured as an attenuator or alternate filter configuration. R5, R6, and C4 form the RC filter between the ADC driver and ADC input that limits the amount of out-of-band noise arriving at the ADC input and attenuates the kickback voltage from the switched capacitors in the ADC’s input. | The design of the data acquisition channel for the EV-HT-200CDAQ1 is covered extensively by the[[adi>CN0365|CN0365]] application note. That design serves as the basis for the three ADC inputs on this platform, although some changes and optimizations were made, mostly in passive component selection, in order to address the form factor requirements of the board and extended reliable operation up to 200°C. The reference acquisition channel circuit is shown the schematic below. There are two “digital multiplexed” channels that each contain a complete data acquisition channel, similar to CN0365, that are capable of running at high sample rates. There is also an “analog multiplexed” channel that adds an ADG798 multiplexer in front of the inputs, optimized for lower throughput inputs. R1 and R3 provide a 1.25 V bias for the non-inverting input of U1, and prevent it from floating to the rail of the analog input if left open, or if the multiplexer is de-selected. R8 and R9 can be changed to increase the gain of U1. R4, R7, and C1 are the anti-aliasing filter, but they can be re-configured as an attenuator or alternate filter configuration. R5, R6, and C4 form the RC filter between the ADC driver and ADC input that limits the amount of out-of-band noise arriving at the ADC input and attenuates the kickback voltage from the switched capacitors in the ADC’s input. |
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| {{ :resources:eval:user-guides:high-temp:ev-ht-200cdaq1:inputchannel.png?nolink |}} | {{ :resources:eval:user-guides:high-temp:ev-ht-200cdaq1:inputchannel.png?nolink |}} |
