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resources:eval:user-guides:adrv9009-zu11eg:adrv2crr-fmc_carrier_board [09 Sep 2021 17:23] – [Power Input] Claudia Gogaresources:eval:user-guides:adrv9009-zu11eg:adrv2crr-fmc_carrier_board [25 Sep 2023 16:13] (current) Brian OLoughlin
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 ---- ----
 ==== FMC Connector ==== ==== FMC Connector ====
-The ADRV2CRR-FMC includes a standard ANSI/VITA 57.1 FMC high-pin count connector. In extension to the standard FMC signals  +The ADRV2CRR-FMC includes a standard ANSI/VITA 57.1 FMC high-pin count connector P1, which is partially populatedFollowing signals are present: 
 +  * 10 serial transceiver lanes FMC_HPC_DPx, 2x serial transceiver reference clock FMC_HPC_GBTCLKx 
 +  * 34 differential IO pairs FMC_HPC_LAx, 2 differential clocks FMC_HPC_CLK0/1_M2C 
 +  * JTAG, I2C interfaces 
 + 
 + 
 +FMC HA and HB differential signals are not populated with user-defined digital IOs as specified in the FMC HPC standard. Instead, RF reference clock signals, synchronization signal, and ADRV9009 IOs are connected to these positions to enhance the capability of the P1 connector by providing the possibility: 
 +  * to add extra ADRV9009 transceivers to the system, and synchronize these with the RF-SOM. This is accomplished with the [[adi>AD-FMCOMMS8-EBZ]] 
 +  * to design custom RF boards that make use of the analog and digital ADRV9009 IOs. 
 + 
 +<note important>All the previous mentioned ADRV9009 IOs, and reference clocks are connected to P1 through 0 Ohm jumpers (JP8-JP91). If an FMC mezzanine card is connected, which conflicts with these signals remove the 0 Ohm jumpers. For the synchronization signal SYNC_OUT2 remove R21 </note> 
 + 
 ---- ----
 ==== IO Expansion Connector ==== ==== IO Expansion Connector ====
 +IO expansion connector P25 is a 2.54mm pitch 2x10mm female connector that gives access to 12 single-ended (6 differential pairs) general purpose IOs, connected to high-performance ZU11EG PL bank 65. The expansion IOs are referenced to 1.8V.  If other levels are needed voltage level translators need to be used.
 ---- ----
 +==== PMOD Connector ====
 +PMOD connector P10, is a 2x6 pin, low-speed host interface, referenced to 3.3V.
 +<note important> Fairchild FXLA108 bidirectional voltage level translator is used on the PMOD signals, to connect these to the 1.8V referenced ZU11EG PL banks. The FXLA108 has auto direction sensing, and might not work properly with some signals, like bidirectional SPI data lines, or open-drain signals. </note>
 +----
 +
 ==== Interfaces ==== ==== Interfaces ====
 The following table outlines levels of functionality provided in software for the I/O interfaces on the carrier board. The following table outlines levels of functionality provided in software for the I/O interfaces on the carrier board.
  
 {{:resources:eval:user-guides:adrv9009_zu11eg:carrier_io.png|}} {{:resources:eval:user-guides:adrv9009_zu11eg:carrier_io.png|}}
----- 
-==== Clock Inputs ===== 
----- 
-==== Fan Control ==== 
----- 
-==== Audio ==== 
 ---- ----
  
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 <WRAP round download> <WRAP round download>
-    * {{:resources:eval:user-guides:adrv9009_zu11eg:carrier_board_02_048950a_top.pdf|Rev A Schematics}} +  * {{:resources:eval:user-guides:adrv9009-zu11eg:02-048950-01-c2_1_.pdf |Rev C.1 Schematics}} 
-    * {{:resources:eval:user-guides:adrv9009_zu11eg:carrier_board_02_048950b_top.pdf|Rev B Schematics}} +  * {{ :resources:eval:user-guides:adrv9009-zu11eg:rev_c.1_bom.zip |Rev C.1 BOM}} 
-    * {{:resources:eval:user-guides:adrv9009_zu11eg:02-048950-01-c.pdf|Rev C Schematics}} +  * {{:resources:eval:user-guides:adrv9009-zu11eg:revc_to_revc.1_errata.xlsx |Rev C to Rev C.1 Errata}} 
-    * {{:resources:eval:user-guides:adrv9009_zu11eg:05-048950-b_BOM.zip|Rev B BOM}} +  * {{ :resources:eval:user-guides:adrv9009-zu11eg:letter_of_volatility_adrv2crr-fmc_carrier_board.pdf|Letter of Volatility}}
-    * {{:resources:eval:user-guides:adrv9009_zu11eg:05-048950-01-c.zip|Rev C BOM}} +
-    * {{:resources:eval:user-guides:adrv9009_zu11eg:08_048950c_BRD.zip|Rev B/BRD File}} +
-    * {{:resources:eval:user-guides:adrv9009_zu11eg:20_048950c_archive.zip|Rev C Board Design Files}}+
 </WRAP> </WRAP>
 +
 +<WRAP round download>
 +  * {{:resources:eval:user-guides:adrv9009_zu11eg:02-048950-01-c.pdf|Rev C Schematics}}
 +  * {{:resources:eval:user-guides:adrv9009_zu11eg:05-048950-01-c.zip|Rev C BOM}}
 +  * {{:resources:eval:user-guides:adrv9009_zu11eg:08_048950c_BRD.zip|Rev B/C BRD File}}
 +  * {{:resources:eval:user-guides:adrv9009_zu11eg:20_048950c_archive.zip|Rev C Board Design Files}}
 +</WRAP>
 +
 +<WRAP round download>
 +  * {{:resources:eval:user-guides:adrv9009_zu11eg:carrier_board_02_048950b_top.pdf|Rev B Schematics}}
 +  * {{:resources:eval:user-guides:adrv9009_zu11eg:05-048950-b_BOM.zip|Rev B BOM}}
 +  * {{:resources:eval:user-guides:adrv9009_zu11eg:08_048950c_BRD.zip|Rev B/C BRD File}}
 +</WRAP>
 +
 +<WRAP round download>
 +  * {{:resources:eval:user-guides:adrv9009_zu11eg:carrier_board_02_048950a_top.pdf|Rev A Schematics}}
 +</WRAP>
 +
 ==== Switches/Jumpers ==== ==== Switches/Jumpers ====
  
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   * USB PHY configuration (the only supported configuration)   * USB PHY configuration (the only supported configuration)
 {{ :resources:eval:user-guides:adrv9009_zu11eg:jmp_usb.png?200 |}} {{ :resources:eval:user-guides:adrv9009_zu11eg:jmp_usb.png?200 |}}
-  * Power good bypass jumpers (P18, P20) - Position 2-3 overrides the power good signal+  * Power good jumpers (P18, P20) (the only working configuration)
 {{ :resources:eval:user-guides:adrv9009_zu11eg:jmp_pgood.png?200 |}} {{ :resources:eval:user-guides:adrv9009_zu11eg:jmp_pgood.png?200 |}}
  
 [[/resources/eval/user-guides/adrv9009-zu11eg|Link to Main Page for ADRV9009-ZU11EG]] [[/resources/eval/user-guides/adrv9009-zu11eg|Link to Main Page for ADRV9009-ZU11EG]]
resources/eval/user-guides/adrv9009-zu11eg/adrv2crr-fmc_carrier_board.1631201008.txt.gz · Last modified: 09 Sep 2021 17:23 by Claudia Goga