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--- resources:eval:user-guides:adin1300-and-adin1200:phy_faq [27 May 2021 20:33] – [Conformance testing] Catherine Redmond
+++ resources:eval:user-guides:adin1300-and-adin1200:phy_faq [16 Jan 2023 10:37] (current) – Added section for MDI pins in Unpowered device Mark Bolger
@@ Line 1: / Line 1: @@
 ====== ADIN1200/ADIN1300 Frequently Asked Questions ======
-{{:resources:eval:user-guides:adin1300-and-adin1200:phy.jpg?400|}}
+{{ :resources:eval:user-guides:adin1300-and-adin1200:phy.jpg?nolink&400 |}}
 ==== Key Considerations when selecting an Industrial PHY ====
@@ Line 12: / Line 12: @@
 ----
+==== Differences between ADIN1200 & ADIN1300 ====
+The key differences are package size, speed, supply rails and feature set.
+{{ :resources:eval:user-guides:adin1300-and-adin1200:phy_compare.jpg?nolink&800 |}}
+----
 ===== Hardware Strapping Features =====
@@ Line 37: / Line 44: @@
+===== Timing / Latency Maximum Receive Time =====
+The Receive latency numbers quoted in Table 1 from the Datasheet are measured from start of data at MDI to the positive edge from RGMII.RXCLK. These are following the MDI to MII/GMII delay constraint definitions in Table 24-2/3 in IEEE Std 802.3 for 100BASE-TX and Table 40-14 for 1000BASE-T, extended to 10BASE-T and RMII/RGMII using the same reference points, i.e.
+  * TX_EN/TX_CTL sampled with the rising edge of TX_CLK/TXC/REF_CLK to 1st bit/symbol on MDI
+  * 1st bit/symbol on MDI to RX_DV sampled with the rising edge of RX_CLK/RXC/REF_CLK
+----
 ===== Resistor Values for Hardware pin config =====
@@ Line 141: / Line 156: @@
 ===== Longer cable length? =====
-As specified in the datasheet, the ADIN1200 supports cable lengths as long as 180m. Limited additional experimental data suggests it can operate out to 210m over CAT5 cable with the default configuration settings.
+The ADIN1300 can support cable lengths up to 150 meters at Gigabit speeds and 180 meters when operating at 100 Mbps or 10 Mbps.
+The ADIN1200 supports cable lengths as long as 180m. Limited additional experimental data with the ADIN1200 suggests it can operate out to 210 meters (at 100 Mbps) over CAT5 cable with the default configuration settings.
+----
+===== 1588 Start of Packet Programmable Delays =====
+The ADIN1200 & ADIN1300 provide hardware pins for Start of Packet indication based on the SFD in the ethernet frame. This function is programmable in terms of which pins are used to provide the indication for Tx and Rx side. See datasheet for full detail on register programmability.
+One element of programmability is the delay
+=== SopTxDelay Delay Register ===
+The SopTxDel delay register is provided to align the TX_SOP signal on the chip pins to the TX SOP on the MDI pins. Jitter should be within ± 4ns by design for all speeds. Using TX_SOP makes more sense for the TX path since it would remove any variable PHY delays, which would happen depending on the speed/MAC interface mode, e.g., in the ADIN1300/1200:
+  - In 1000BASE-T for any MAC interface (GMII/RGMII).
+  - In 100BASE-TX and 10BASE-T for RGMII interface.
+The recommended SopTxDel values (called out in the datasheet register documentation) would align the TX_SOP signal to the SOP signal on the MDI pins.
+{{ :resources:eval:user-guides:adin1300-and-adin1200:soptx.png?nolink&600 |}}
+=== SopRxDelay Delay Register ===
+RX_SOP is less useful in general, since there is only a variable PHY delay in the RX path in ADIN1300/1200 when the RMII interface is used (100BASE-TX or 10BASE-T).
+In all other cases, there is no variable delay in the RX path, and therefore the SOP signal can be extracted at the MAC side. The timing between RX_SOP and the MAC side RX SOP (RX_DV=1, RXD = 0xD5) sampled on the rising edge of RX_CLK) would be fixed (See figure below). But since the RX MAC interface signals are synchronous to RX_CLK, while RX_SOP is not, the later would have to be re-synchronized to the MAC clock, so it might have in fact less precision (depending on the MAC implementation).
+The t1 value would be independent of the MAC interface (MII/GMII/RGMII/RMII). The values (from simulation) are:
+-	In 100BASE-TX: t1 = 260 ns
+-	In 1000BASE-T: t1 = 212 ns
+The RX_SOP signal at the chip pin will have some additional delay, due to the internal routing and the I/O cell delay, which will be heavily dependent on the loading and PVT, estimate for that delay to be somewhere between 2 ns and 6 ns.
+The SopRxDel delay does not make so much sense in general for ADIN1200/1300. Given that the RX SOP on the MDI pins will happen before the RX_SOP signal on the chip pin, to align both signals (as done in the TX side), it would be required to advance the RX_SOP signal rather than delay it, but that is obviously not possible. Therefore, the SopRxDel delay was intended for a different purpose, it is provided for cases where there may be a very long latency in the MAC interface (for example if the PHY had an SGMII interface) to ensure that the RX_SOP signal is received at the MAC side during the corresponding frame, as if that was not the case it might cause problems.
+{{ :resources:eval:user-guides:adin1300-and-adin1200:soprx.png?nolink&600 |}}
+----
+===== Voltage Mode Line Drive =====
+The ADIN1200 & ADIN1300 are voltage mode with on chip terminations. Therefore, there is no need for external termination resistors from the center tap of the transformer to the supply as required in current mode line drivers.
+In addition to reducing components, Voltage mode driver also manifests a significant reduction in power consumption versus current mode.
+When comparing PHY devices, ensure to check whether the output stage is voltage mode or current mode and also review whether the power consumption figures for current mode include the current dissipated in the transformer as a result of termination resistors.
+----
+===== Connecting a Cable to an Unpowered Device =====
+The ADIN1300 and ADIN1200 have internal protection circuitry on the MDI pins that will protect them from damage when standard ethernet traffic is sent into an unpowered device from a remote active device.
+----
+===== Do the Exposed Pad and Bus Bars have to be soldered down? =====
+The LFCSP has an exposed pad underneath the package that must be soldered to the PCB ground for electrical, mechanical and thermal reasons. For thermal impedance performance and to maximize heat removal, use of a 4 × 4 array of thermal vias beneath the exposed ground pad is recommended.
+There are also two bus bars on either side of the exposed pad, these bus bars are connected to internal voltage rails and are **not** intended to, and should **not** be soldered to the board. The PCB land pattern must incorporate the exposed ground paddle with vias and two keep out areas around the bus bars in the footprint. No PCB traces or vias can be used in either of the keep out areas. The EVAL-ADIN1300FMCZ uses an array of 4 × 4 vias on a 0.75 mm grid arrangement, as shown in the figure below. The via pad diameter dimension is 0.02 in. (0.5015 mm) and the finished drill hole diameter is 0.01 in. (0.2489 mm). This also applies to the exposed pad and bus bars for the ADIN1200. See the ADIN1200 Datasheet for the equivalent figure relating to the different package size.
+{{ :resources:eval:user-guides:adin1300-and-adin1200:adin1300_paddle_and_keep_out_areas.png |}}

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