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--- resources:eval:user-guides:ad9213_dual_ebz:ad9213_dual_ebz_hdl [28 Mar 2022 09:37] – Add notes regarding capture limitations Adrian Costina
+++ resources:eval:user-guides:ad9213_dual_ebz:ad9213_dual_ebz_hdl [12 Apr 2022 10:13] – Explicitly state the S10SOC version Adrian Costina
@@ Line 18: / Line 18: @@
 ==== Supported Carriers ====
-  * [[intel>Stratix10SOC]] FMC+ Slots
+  * [[https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/stratix/10-sx.html |S10SOC(DK-SOC-1SSX-H-D)]]
 ==== Building the HDL project ====
@@ Line 29: / Line 29: @@
 The design has two JESD receive chains each having 16 lanes at rate of 12.5Gbps.
 The JESD receive chain consists of a physical layer represented by an XCVR module, a link layer represented by an RX JESD LINK module. The transport layer is common and is represented by a RX JESD TPL module.
-The links operate in Subclass 1 by using the SYSREF signal to edge align the internal local multiframe clock and to release the received data in the same moment from all lanes. Therefore ensuring that data from all channels is synchronized at the application layer.
+The links operate in Subclass 1 by using the SYSREF signal to edge align the internal local multiframe clock and to release the received data in the same moment from all lanes, therefore ensuring that data from all channels is synchronized at the application layer.
 Both links are set for full bandwidth mode and operate with the following parameters:

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