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resources:eval:user-guides:ad7768-1 [22 Oct 2020 13:36] – [No-OS Downloads] wasim shaikhresources:eval:user-guides:ad7768-1 [09 Jan 2021 00:32] (current) – user interwiki links Robin Getz
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 ==== Supported FPGA carrier ==== ==== Supported FPGA carrier ====
-  * [[http://www.xilinx.com/products/boards-and-kits/1-8dyf-11.html|ZedBoard]] +  * [[xilinx>products/boards-and-kits/1-8dyf-11.html|ZedBoard]] 
  
 ===== HDL Design Description ===== ===== HDL Design Description =====
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 In the [[:resources/fpga/docs/hdl|ADI Reference Designs HDL User Guide]] can be found an in-depth presentation and instructions about the HDL design in general. In the [[:resources/fpga/docs/hdl|ADI Reference Designs HDL User Guide]] can be found an in-depth presentation and instructions about the HDL design in general.
  
-The reference design uses the standard [[https://wiki.analog.com/resources/fpga/peripherals/spi_engine|SPI Engine Framework]], the offload module is triggered by the DRDY (data ready) signal of the device. Because the board has two AD7768-1, the data path consists of two separate SPI interface and GPIOs, and two DMAs for data stream capture.+The reference design uses the standard [[/resources/fpga/peripherals/spi_engine|SPI Engine Framework]], the offload module is triggered by the DRDY (data ready) signal of the device. Because the board has two AD7768-1, the data path consists of two separate SPI interface and GPIOs, and two DMAs for data stream capture.
  
 In order to build the HDL design the user has to go through the following steps: In order to build the HDL design the user has to go through the following steps:
resources/eval/user-guides/ad7768-1.txt · Last modified: 09 Jan 2021 00:32 by Robin Getz

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