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--- resources:eval:user-guides:ad713x:hdl [21 Jul 2023 11:32] – Update block diagram Laurentiu Popa
+++ resources:eval:user-guides:ad713x:hdl [31 Jul 2023 08:32] (current) – Laurentiu Popa
@@ Line 36: / Line 36: @@
 The design only supports the slave mode for both devices with both DCLK and ODR generated by the FPGA. Each device sends data on 4 of the 8 DIN bits.
-{{:resources:fpga:docs:ad713x_hdl_4.svg|spi engine block diagram}}
+{{:resources:fpga:docs:ad713x_hdl_6.svg|spi engine block diagram}}
 In order to build the HDL design the user has to go through the following steps:

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