This version (31 Jul 2023 08:32) was approved by Laurentiu Popa.The Previously approved version (13 Apr 2022 10:39) is available.Diff

EVAL-AD7134FMCZ HDL Reference Design


The HDL reference design for the EVAL-AD7134FMCZ provides all the interfaces that are necessary to interact with the device using a Xilinx FPGA development board.

The design has all the necessary infrastructure to acquire data from both AD7134 24-bit 4-channel precision alias free ADC devices, supporting continuous data capture at maximum 1.5 MSPS data rate. The design targeted to the Zedboard, which is a low cost FPGA carrier board from Digilent, using a Zynq-7000 re-programmable SoC from Xilinx.

Used devices

Evaluation board

Supported FPGA carrier

Jumper setup

Jumper/Solder link Position Description
JP14 Mounted DEC0/DCLKIO
JP15 Mounted DEC0/DCLKIO
JP16 Mounted MODE
JP17 Mounted MODE

HDL Design Description

The design is built upon ADI's generic HDL reference design framework. More information about the framework can be found in the ADI Reference Designs HDL User Guide wiki page.

The reference design uses the SPI Engine Framework to interface with the two AD7134 ADCs.

The design only supports the slave mode for both devices with both DCLK and ODR generated by the FPGA. Each device sends data on 4 of the 8 DIN bits.

spi engine block diagram

In order to build the HDL design the user has to go through the following steps:

  1. Confirm that you have the right tools (see Release notes)
  2. Clone the HDL GitHub repository (see

HDL Downloads

Software sources

resources/eval/user-guides/ad713x/hdl.txt · Last modified: 31 Jul 2023 08:32 by Laurentiu Popa