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resources:eval:user-guides:ad-fmcomms4-ebz:hardware [09 Mar 2023 01:49] – updated the Rev. C design files download link Joyce Velasco | resources:eval:user-guides:ad-fmcomms4-ebz:hardware [09 Mar 2023 02:10] – updated the design files download link Joyce Velasco |
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===== Schematic, PCB Layout, Bill of Materials ===== | ===== Schematic, PCB Layout, Bill of Materials ===== |
| ==== Rev. C ==== |
<WRAP round download 65%> | <WRAP round download 65%> |
<WRAP info>Note that the Baluns on the Rev C board (T101-T104) are either: | <WRAP info>Note that the Baluns on the Rev C board (T101-T104) are either: |
* Mini Circuits [[http://www.minicircuits.com/pdfs/TCM1-63AX+.pdf|TCM1-63AX+]]. They are rated for an operating frequency between 70 MHz and 6 GHz, and are connected to the RXA Input and TXB Output. | * Mini Circuits [[http://www.minicircuits.com/pdfs/TCM1-63AX+.pdf|TCM1-63AX+]]. They are rated for an operating frequency between 70 MHz and 6 GHz, and are connected to the RXA Input and TXB Output. |
</WRAP> | </WRAP> |
[[adi>media/en/reference-design-documentation/design-integration-files/ad-fmcomms4-ebz-designsupport.zip|AD-FMCOMMS4-EBZ Rev. C Design & Integration Files]] | [[adi>media/en/reference-design-documentation/design-integration-files/ad-fmcomms4-ebz-designsupport.zip|AD-FMCOMMS4-EBZ Design & Integration Files]] |
* Schematic | * Schematic |
* PCB Layout | * PCB Layout |
</WRAP> | </WRAP> |
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| ==== Rev. B ==== |
<WRAP round download 65%> | <WRAP round download 65%> |
<WRAP info>Note that the Baluns on the Rev B board (T101-T104) are either: | <WRAP info>Note that the Baluns on the Rev B board (T101-T104) are either: |
===== I/O Voltage ===== | ===== I/O Voltage ===== |
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The AD-FMComms4 (AD9364) assumes a VDD_INTERFACE voltage between 1.71V and 2.625V (1.8 to 2.5 +/- 5%), so on your FPGA carrier board, you should ensure that V<sub>ADJ</sub> is between these levels. Setting things to 3.3V will damage the part. | The [[ADI>AD-FMCOMMS4-EBZ]] (AD9364) assumes a VDD_INTERFACE voltage between 1.71V and 2.625V (1.8 to 2.5 +/- 5%), so on your FPGA carrier board, you should ensure that V<sub>ADJ</sub> is between these levels. Setting things to 3.3V will damage the part. |
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