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resources:eval:user-guides:ad-fmcomms2-ebz:reference_hdl [24 Sep 2014 21:46] – [Control and SPI] rejeesh kuttyresources:eval:user-guides:ad-fmcomms2-ebz:reference_hdl [01 Feb 2023 02:07] (current) – Replaced the obsolete Kuiper Linux page link; repaired broken links Joyce Velasco
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- +====== AD9361 HDL Reference Designs ======
-====== AD-FMCOMMS2-EBZ / AD-FMCOMMS3-EBZ / AD-FMCOMMS4-EBZ HDL / AD-FMCOMMS5-EBZ HDL Reference Design ======+
  
 ===== Functional Overview ===== ===== Functional Overview =====
  
-The reference design is a processor based (ARM or Microblaze) embedded system. A functional block diagram of the system is given below. The device interface is a self-contained peripheral similar to other such pcores in the system. The core is programmable through an AXI-lite interface. The data path consists of a VDMA and DMA interface for the transmit and receive path respectively.+The reference design is a processor based (ARM, [[wp>MicroBlaze]], or [[wp>Nios_II|NioS]]) embedded system. A functional block diagram of the system is given below. The device interface is a self-contained peripheral similar to other such pcores in the system. The core is programmable through an AXI-lite interface. The data path consists of a VDMA and DMA interface for the transmit and receive path respectively.
  
  
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 The core supports multiple instances of the same synchronized to a common clock. The ADFMCOMMS5 uses two instances of this core synchronized to a common clock. The data is recovered in each individual clock domain and transfers the data to a single clock domain. The multiple cores must all be using the same clock. The core supports multiple instances of the same synchronized to a common clock. The ADFMCOMMS5 uses two instances of this core synchronized to a common clock. The data is recovered in each individual clock domain and transfers the data to a single clock domain. The multiple cores must all be using the same clock.
- 
- 
  
 ===== Supported Devices ===== ===== Supported Devices =====
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   * [[adi>AD-FMCOMMS4-EBZ]]   * [[adi>AD-FMCOMMS4-EBZ]]
   * [[adi>AD-FMCOMMS5-EBZ]]   * [[adi>AD-FMCOMMS5-EBZ]]
 +  * [[../arradio|ARRADIO]]
 +  * [[../picozed_sdr|PicoZed SDR]]
  
 ===== Supported Carriers ===== ===== Supported Carriers =====
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 These are the supported carriers for the HDL - not the complete package (software and HDL). Typically the software lags behind the HDL, so if you don't see the these listed on the main project page - it is not yet done. These are the supported carriers for the HDL - not the complete package (software and HDL). Typically the software lags behind the HDL, so if you don't see the these listed on the main project page - it is not yet done.
  
-Our recommended plaforms are the Zynq based systems:+For the FMCOMMS2, 3, 4 based boards, supported carriers include the Xilinx Zynq based systems:
   * [[xilinx>ZC702]]    * [[xilinx>ZC702]] 
   * [[xilinx>ZC706]]    * [[xilinx>ZC706]] 
   * [[http://www.zedboard.org|Zed Board]]    * [[http://www.zedboard.org|Zed Board]] 
  
-but it also works on the fabric only solutions (for experts, who have used the zynq based systems in the past).+but it also works on the Xilinx fabric only solutions (for experts, who have used the zynq based systems in the past).
   * [[xilinx>KC705]]    * [[xilinx>KC705]] 
   * [[xilinx>VC707]]    * [[xilinx>VC707]] 
  
 +For Altera SoC based systems and the ARRADIO board, we support [[ :resources:eval:user-guides:arradio| ARRADIO  ]] :
  
-===== Download ======+  * [[https://www.arrow.com/en/products/sockit/arrow-development-tools|SoC Kit]] 
  
-FPGA Reference Designs on GitHub :+===== Download HDL ======
  
-<WRAP round download 80%> +<WRAP round info 100%> 
-  * **Vivado Downloads** +Please note that the projects **FMCOMMS2**, **FMCOMMS3** and **FMCOMMS4** are using the [[https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcomms2|same]] hdl design.  
-  * https://github.com/analogdevicesinc/hdl (This is our main repository and contents change frequently. A release (more stable) branch will be available soon.)+The **ARRADIO** Quartus project uses [[https://github.com/analogdevicesinc/hdl/tree/master/projects/arradio/c5soc|Arradio]] hdl design. 
 +</WRAP>
  
- +{{page>/resources/fpga/docs/hdl/downloads_insert#fmcomms2fmcomms3fmcomms4&nofooter&noeditbtn}} 
-  * **XPS/EDK Downloads** +{{page>/resources/fpga/docs/hdl/downloads_insert#fmcomms5&nofooter&noeditbtn}} 
-  * https://github.com/analogdevicesinc/fpgahdl_xilinx/archive/ad_fmcomms2_ebz_edk_14_4_2013_10_22.tar.gz +{{page>/resources/fpga/docs/hdl/downloads_insert#arradio&nofooter&noeditbtn}}
-  * https://github.com/analogdevicesinc/fpgahdl_xilinx/archive/ad_fmcomms2_ebz_edk_14_4_2013_10_22.zip +
- +
-  * **Previous Releases & Tags** +
-  * https://github.com/analogdevicesinc/fpgahdl_xilinx/tags +
-  * https://github.com/analogdevicesinc/fpgahdl_xilinx/releases +
- +
-  * **Git Repository** +
-  * https://github.com/analogdevicesinc/fpgahdl_xilinx.git +
-</WRAP>+
  
 <WRAP round help 80%> <WRAP round help 80%>
-  * Questions? [[http://ez.analog.com/post!input.jspa?containerType=14&container=2061|Ask Help & Support]].+  * Questions? [[/resources/eval/user-guides/ad-fmcomms2-ebz/help_and_support|Ask Help & Support]].
 </WRAP> </WRAP>
  
 ===== Generating Xilinx netlist files ====== ===== Generating Xilinx netlist files ======
  
-The repository will not contain Xilinx netlist files, only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details. +The repository will not contain Xilinx netlist files, only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details.
  
-{{navigation AD-FMCOMMS2-EBZ#Hardware#.:|Overview#Software}} 
resources/eval/user-guides/ad-fmcomms2-ebz/reference_hdl.1411587997.txt.gz · Last modified: 24 Sep 2014 21:46 by rejeesh kutty

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