The reference design is a processor based (ARM, MicroBlaze, or NioS) embedded system. A functional block diagram of the system is given below. The device interface is a self-contained peripheral similar to other such pcores in the system. The core is programmable through an AXI-lite interface. The data path consists of a VDMA and DMA interface for the transmit and receive path respectively.
The digital interface consists of 12bits of DDR data and supports full duplex operation in all configurations up to 2×2. The transmit and receive data paths share a single clock. The data is sent or received based on the configuration (programmable) from separate transmit and to separate receive chains.
In the transmit direction, complex I and Q signals are generated for each RF. The digital source could either be an internal DDS or from the external DDR via VDMA. The internal DDS phase and frequency are programmable.
In the receive direction, each component of the delineated data is passed to a PN monitor. The monitors validates the digital interface signal capture and timing. The data then optionally DC-filtered, corrected for I/Q offset and phase mismatches and is written to the external DDR memory via DMA. An optional off-line FFT core may be used to generate a spectrum plot.
The device control and monitor signals are interfaced to a GPIO module. The SPI signals are controlled by a separate AXI based SPI core.
The core supports multiple instances of the same synchronized to a common clock. The ADFMCOMMS5 uses two instances of this core synchronized to a common clock. The data is recovered in each individual clock domain and transfers the data to a single clock domain. The multiple cores must all be using the same clock.
These are the supported carriers for the HDL - not the complete package (software and HDL). Typically the software lags behind the HDL, so if you don't see the these listed on the main project page - it is not yet done.
For the FMCOMMS2, 3, 4 based boards, supported carriers include the Xilinx Zynq based systems:
but it also works on the Xilinx fabric only solutions (for experts, who have used the zynq based systems in the past).
For Altera SoC based systems and the ARRADIO board, we support ARRADIO :
|Hardware||Project||Carriers||Resource Utilization||Library Cores|
The repository will not contain Xilinx netlist files, only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See generating Xilinx netlist/verilog files from xco files for details.