This version (13 Dec 2016 11:09) was approved by LucianS.The Previously approved version (02 May 2016 17:38) is available.Diff

AD9361 HDL Reference Designs

Functional Overview

The reference design is a processor based (ARM, MicroBlaze, or NioS) embedded system. A functional block diagram of the system is given below. The device interface is a self-contained peripheral similar to other such pcores in the system. The core is programmable through an AXI-lite interface. The data path consists of a VDMA and DMA interface for the transmit and receive path respectively.

Block diagram

Digital Interface

The digital interface consists of 12bits of DDR data and supports full duplex operation in all configurations up to 2×2. The transmit and receive data paths share a single clock. The data is sent or received based on the configuration (programmable) from separate transmit and to separate receive chains.


In the transmit direction, complex I and Q signals are generated for each RF. The digital source could either be an internal DDS or from the external DDR via VDMA. The internal DDS phase and frequency are programmable.


In the receive direction, each component of the delineated data is passed to a PN monitor. The monitors validates the digital interface signal capture and timing. The data then optionally DC-filtered, corrected for I/Q offset and phase mismatches and is written to the external DDR memory via DMA. An optional off-line FFT core may be used to generate a spectrum plot.

Control and SPI

The device control and monitor signals are interfaced to a GPIO module. The SPI signals are controlled by a separate AXI based SPI core.

Multi-Cores Operation (ADFMCOMMS5)

The core supports multiple instances of the same synchronized to a common clock. The ADFMCOMMS5 uses two instances of this core synchronized to a common clock. The data is recovered in each individual clock domain and transfers the data to a single clock domain. The multiple cores must all be using the same clock.

Supported Devices

Supported Carriers

These are the supported carriers for the HDL - not the complete package (software and HDL). Typically the software lags behind the HDL, so if you don't see the these listed on the main project page - it is not yet done.

For the FMCOMMS2, 3, 4 based boards, supported carriers include the Xilinx Zynq based systems:

but it also works on the Xilinx fabric only solutions (for experts, who have used the zynq based systems in the past).

For Altera SoC based systems and the ARRADIO board, we support ARRADIO :

Download HDL

Please note that the projects FMCOMMS2, FMCOMMS3 and FMCOMMS4 are using the same hdl design. The ARRADIO Quartus project uses Arradio hdl design.


Hardware Project Carriers Library Cores
ARRadio arradio c5soc

Download Linux Image

The BOLD is what you should type. It's not too much more than Special Agent Oso's three special steps, and it also allows you to go for that specialty coffee you have been craving.

For different platforms you'll need different images. Currently we provide a single pre-build images, that can work on all the platforms we support.

  • 23 December 2016 release (2016_R1)
  • Checksum 2016_R1-2016_12_23.img.xz f167bfad87f9b9856d3b94297385a375
  • Checksum 2016_R1-2016_12_23.img edf8ea425576c9dd913e74e44c404e04
  • 12 December 2016 release (2016_R1)
  • Checksum 2016_R1-2016_12_12.img.xz fdc2cd4d4075933ea7817f23544ca85e
  • Checksum 2016_R1-2016_12_12.img efc43e1b372bf154e8c4a11c5de8de22
  • 26 July 2016 release (2015_R2)
  • Checksum 2015_R2-2016_07_26.img.xz 1520D974FBAADA6107B4C41606C40264
  • Checksum 2015_R2-2016_07_26.img E0D5748101D476FCA807C20EEF03E788
  • 1 April 2016 release (2015_R2)
  • Checksum 2015_R2-2016_04_01.img.xz 25AE4DCB2B86C8AC00BD571304670BF5
  • Checksum 2015_R2-2016_04_01.img 3298D9FD4104A001C8F72D94FC28304C
  • 15 March 2016 release (2015_R2)
  • Checksum 2015_R2-2016_03_15.img.xz F6CCE2437B2CAA54F882B3DF1C49B9E2
  • Checksum 2015_R2-2016_03_15.img E9BD5C4111C2D9F43FC55F7B44BD10F8
  • 22 December 2015 release (2015_R1)
  • Checksum 2015_R1-2015_12_22.img.xz a8f3ed68625043e180c95677123794bd
  • Checksum 2015_R1-2015_12_22.img fd1e4154e59e7dc62e508a4cdc522db5
  • 17 November 2015 release (2015_R1)
  • Checksum 2015_R1-2015_11_17.img.xz 19d9d3bb934f7971655475f2a1dd4f07
  • Checksum 2015_R1-2015_11_17.img 827da115f5620bee5feaee52d764af10
  • 4 September 2015 release (2015_R1)
  • Checksum 2015_R1-2015_09_04.img.xz 3D2377CF5264649C899DD98027E11992
  • Checksum 2015_R1-2015_09_04.img 8B4244D5848E9414FF0B79344F4601F2
  • 31 August 2015 release (2015_R1)
  • Checksum 2015_R1-2015_08_31.img.xz EFA6C36E0A79FDDEB2913069EDDD237F
  • Checksum 2015_R1-2015_08_31.img F7EC381FDF519945C975FF3D2B57AB36
  • 6 February 2015 release (2014_R2)
  • Checksum 2014_R2-2015_02_06.img.xz bb76031fcd68fd9b1a175a2f7fd3e053
  • Checksum 2014_R2-2015_02_06.img 132d03a2888db34f10f0ebbcb3100ae7

Now, depending if you are using Linux or Windows, follow these instructions to write the file to your 8 Gig SD card.

02 Sep 2015 18:41 · Dragos Bogdan
18 Mar 2016 15:24 · Lucian Sin

Generating Xilinx netlist files

The repository will not contain Xilinx netlist files, only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See generating Xilinx netlist/verilog files from xco files for details.

resources/eval/user-guides/ad-fmcomms2-ebz/reference_hdl.txt · Last modified: 13 Dec 2016 11:09 by LucianS