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This particular articl/edocument/design has been retired or deprecated, which means it is no longer maintained or actively updated, even though the devices themselves may be Recommended for New Designs or in Production. This page is here for historical/reference purposes only.
This design is targeted for Zynq based FPGA systems.
The reference design contains HDL blocks for interfacing with the various components of the motor control hardware:
All the HDL blocks connect to Chipscope ILA and VIO modules which provide the means to monitor and control their operation.
Details about the Chipscope interface and how to run the ISE project can be found in the ISE Project with Chipscope Quick Start Guide.