This is an old revision of the document!
Xilinx ISE HDL Reference Design
This design is targeted for Zynq based FPGA systems.
The reference design contains HDL blocks for interfacing with the various components of the motor control hardware:
ADC Interface - Implements the communication with the AD7401 sigma delta modulators present on the AD-FMCMOTCON1-EBZ and also the SINC3 filters for demodulating the 1-bit digital stream provided by these parts.
Controller - Implements the motor control algorithm. The algorithm is designed and simulated in Simulink from Matworks and afterwards translated to HDL using the Mathworks HDL Coder.
Speed Sensor Interface - Implements the algorithm for converting Hall, BEMF and Encoder signals into speed and position data.
All the HDL blocks connect to Chipscope ILA and VIO modules which provide the means to monitor and control their operation.
Details about the Chipscope interface and how to run the ISE project can be found in the ISE Project with Chipscope Quick Start Guide.