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resources:eval:dpg:ad9739-ebz [26 Jun 2012 16:46] – [SPI Settings and Powerdown/Reset] Michael Fowler | resources:eval:dpg:ad9739-ebz [28 Sep 2021 07:26] – Update to SDPH1 and ADSV7 Melissa Lorenz Lacanlale | ||
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- | ====== AD9739 | + | ======EVALUATING THE AD9739 |
- | ===== Getting Started with the AD9122 Evaluation Board ===== | + | |
- | ==== What's in the Box ==== | + | |
- | * AD9739-EBZ | + | =====Preface===== |
- | * Mini-USB Cable | + | This user guide describes both the hardware and software setup needed to acquire data capture from [[adi> |
- | | + | |
- | ==== Recommended Equipment | + | This guide shows how AD9739-R2-EBZ works with SDP-H1 or ADS7-V2 controller board developed by Analog Devices. Link to the previous user guide document is provided for customers who still have the DPG3 controller board. |
- | * Digital Pattern Generator (DPG2): ADI HSC-DAC-DPG-BZ | + | |
- | * +5Vdc Power Supply Ex: Agilent E3630A | + | =====Typical Setup===== |
- | * Low Phase Noise Clock Source or ADF4350 Evaluation Board | + | {{ :resources: |
- | * Spectrum Analyzer Ex: Agilent PSAA or Rohde Schwarz FSU | + | <WRAP centeralign>// |
- | * PC: Windows PC with 2 or more USB ports | + | |
- | ==== Introduction | + | {{ :resources: |
- | The AD9739 Evaluation Board connects to the Analog Devices Digital Pattern Generator (DPG2) to allow for quick evaluation of the AD9739. The DPG2 allows the user to create many types of digital vectors | + | <WRAP centeralign>// |
- | ==== Software Installation ==== | + | |
- | The DAC Software Suite plus AD9739 Update should be installed on the PC prior connecting the hardware to the PC. The DAC Software Suite is included on the Evaluation Board CD, or can be downloaded from the DPG web site at http://www.analog.com/dpg. This will install DPGDownloader (for loading vectors into the DPG2) and the AD9739 SPI Controller application. | + | <note tip>Tip: Click on any picture in this guide to open an enlarged version.</ |
- | ==== Hardware Setup ==== | + | |
- | To operate the board, a power supply capable | + | |
- | ==== Evaluation Board Editions ==== | + | =====Helpful Files:===== |
- | The AD9739 Evaluation Board has four versions: “Normal” (AD9739-EBZ), “Mix Mode” (AD9739-MIX-EBZ), and “CMTS” (AD9739-CMTS-EBZ) and the newer AD9739-R2-EBZ. | + | * Download |
- | <note important> | + | * Data Sheet: |
- | The four editions differ only in the output stage configuration. The software used to evaluate all four boards is identical.</note> | + | * IBIS Model: [[adi> |
- | === R2 === | + | * Schematic: {{ : |
- | The new R2 board is designed to allow evaluation of the AD9739 | + | * Bill of Materials: {{ : |
- | === Normal | + | |
- | In normal mode, there is no filter and the only components are the 90Ω resistors to terminate the DAC outputs and the two transformers | + | |
- | (balun and center tap) as shown in Figure 3. (All customers should now use the AD9739-R2-EBZ board) | + | * PCB Gerber files: {{ : |
- | === Mix-Mode | + | |
- | The Mix-Mode configuration is targeted at applications using the 2nd and 3rd Nyquist zones using the analog mix mode. In this application, | + | * PCB BRD file: [[ftp:// |
- | === CMTS === | + | |
- | This configuration was for applications targeting cable infrastructure applications up to 1GSPS. | + | * PCB Layout PDF: {{ : |
- | ===== Getting Started | + | |
- | This quick-start will setup a single-tone output from the AD9739 to provide a brief introduction | + | =====Software Needed:===== |
- | ==== Enable Mu Controller ==== | + | * [[: |
- | In order to optimize | + | * [[: |
- | {{ : | + | |
- | ==== Generating a Test Vector ==== | + | =====Hardware Needed:===== |
- | Open DPGDownloader (Start | + | * [[adi> |
- | Click on Add Generated Waveform, and then Single Tone, as shown below. A Single Tone panel will be added to the vector list. Start by entering the Clock Frequency | + | * [[: |
- | {{ : | + | * [[adi> |
- | After the DPG2 is correctly setup, click the Download | + | * 5Vdc 2A Power Supply |
- | ==== Enable LVDS Controller | + | * PC with ACE and DPG Lite Software Applications |
- | Once the pattern is loaded into the DPG2 and running, | + | * High-Frequency Continuous Wave Generator |
- | {{: | + | * Signal/ |
+ | * USB-A to USB-Mini Cable | ||
+ | * (2) SMA Cables | ||
+ | * Power Supply to SMA cable | ||
+ | * The following are included | ||
+ | * 12Vdc 2.5A Wall Wart | ||
+ | * USB-A to USB-Mini Cable | ||
+ | * The following are included | ||
+ | * 12V 60W AC/DC Power Supply | ||
+ | * Power Cord | ||
+ | * USB-A to USB-B Cable | ||
+ | |||
+ | =====Quick Start Guide===== | ||
+ | - Attach | ||
+ | * If using **SDP-H1**, set clock input to **300 MHz and 0 dBm**. Connect SDP-H1 | ||
+ | * If using **ADS7-V2**, | ||
+ | - Open ACE. The board will automatically | ||
+ | * If using **SDP-H1**, The MU Controller | ||
+ | * If using **ADS7-V2**, The first three indicators should light up as shown in figure 2b. <WRAP centeralign> | ||
+ | - Double click the AD9739 Box to open chip view. | ||
+ | * If using **SDP-H1**, The DLL_LOCKED indicator should light up as shown in figure 3a. | ||
+ | * If using **ADS7-V2**, | ||
+ | - Start DPG Lite or DPG Downloader. | ||
+ | * At the SDP-H1 settings, ensure that Evaluation board is equal to AD9739 and **DCO frequency** of around **75 MHz** should be displayed. | ||
+ | * At the ADS7-V2 settings, ensure that Evaluation board is equal to AD9739 | ||
+ | - In DPG Lite or DPG Downloader, from the **Add Generator Waveforms** pulldown menu, select **Single Tone** and apply the settings | ||
+ | * When using SDP-H1, set **Data Rate** | ||
+ | * When using ADS-V2, set **Data Rate** to 2 GHz and **Desired Frequency** to 180 MHz. | ||
+ | - Continuing on setting up DPG Lite or DPG Downloader, | ||
+ | - Select | ||
+ | - Press the download arrow and then the play button. The FFT plots similar to Figures 5a and 5b should appear in the signal/ | ||
+ | |||
+ | |||
+ | =====Troubleshooting===== | ||
+ | This section lists items to check and practices to use when debugging any unexpected performance of a board. If unexpected results occur: | ||
+ | * Check if the Voltage supply test points of the evaluation board has the correct value. | ||
+ | * Check if all (3) blue LEDs on the AD-DAC-FMC-ADP board is lit up. Reconnect the board to the FMC connector of SDP-H1 if not lit up. | ||
+ | * Check if the SDP-H1 is being supplied properly by 12Vdc adaptor. Some LEDs on the SDP-H1 should lit up. | ||
+ | * Power cycle both the SDP-H1/ | ||
+ | * Check on the Spectrum Analyzer if the DAC clock inputs are properly driven. For 300MHz clock using SDP-H1, | ||
+ | * Disconnect and reconnect the SDP-H1 /ADS7-V2 and AD9739 evaluation board. Reopen DPG Lite software. | ||
- | {{ : | ||
- | ==== Result ==== | ||
- | The final result of this setup should be as shown below. | ||
- | {{ : | ||
- | ===== SPI Controller ===== | ||
- | The SPI controller software is broken up into numerous sections. Several of them are described here, as they pertain to the evaluation board. For complete descriptions of each SPI register, see the AD9739 datasheet. In the interest of continuous quality improvements, | ||
- | ==== SPI Settings and Powerdown/ | ||
- | {{ : | ||
- | These bits (shown to the right) control the operation of the SPI port on the AD9739, as well as the master reset and individual power-down bits. Changing the SDIO DIR or DATADIR bits will cause the SPI controller application to stop functioning correctly. Do not change these bits. The Reset button is “sticky”, | ||
- | ==== Controller Clock Controls and Analog FS controls ==== | ||
- | The Controller Clock controls enable the Mu Controller and LVDS controllers. For normal operation, | ||
- | both of these should be enabled. The Clock GEN PDswitch powers down the clocking structure, and | ||
- | should be left disabled for normal use. | ||
- | The DAC current ouput has an adjustable full-scale value. The FSC Setoption allows for this adjustment. | ||
- | After running the SPI controller, the full-scale current in miliamps will be displayed here. | ||
- | Mu Controller Clock Enable: Register 0x02 Bit 0 | ||
- | LVDS Controller Clock Enable: Register 0x02 Bit 1 | ||
- | Analog Full-Scale Setting (10 bit Gain DAC 10-30mA adjustment): | ||
- | 0x07 bits 0,1 | ||
- | ==== Decoder Controller and IRQ Controls ==== | ||
- | Decoder Mode: Register 0x08 Bits 0,1 | ||
- | 0x0 – Normal Mode | ||
- | 0x1 – Return to zero (RZ) Mode | ||
- | 0x2 – Mix Mode | ||
- | ==== Cross Control ==== | ||
- | CLKP Offset Setting: Register 0x24 Bits 0-3 | ||
- | CLKP Direction Bit: Register 0x24 Bit 4 | ||
- | CLKP Offset Setting: Register 0x25 Bits 0-3 | ||
- | CLKP Direction Bit: Register 0x25 Bit 4 | ||
- | Damp: Register 0x25 Bits 7 | ||
- | Mu Controller Enable: Register 0x26 Bit 0 (Set to 1 to enable the controller) | ||
- | Mu Controller Gain: Register 0x26 Bits 1,2 (Optimal Setting is a Gain of 1) | ||
- | MU Desired Phase: Desired Phase Value for Phase to Voltage Converter to Optimize Mu Controller. The | ||
- | optimal setting is negative 6 (max of 16) . Register 0x27 bits 0-4 | ||
- | Slope: Slope the mu contoller will lock onto Register 0x26 bit 6 (Optimal setting is Negative slope set bit to 0) | ||
- | MU_DEL_Manual: | ||
- | search. It is best to set it to the middle of the delay line . The maximum Mu delay is 432, so set these bits to | ||
- | approximately 220. | ||
- | Mode: Register: 0x26 Bits 4, 5 Sets the Mode in which the Controller searches: | ||
- | 0x00 – Search and Track (Optimal Setting) | ||
- | 0x01 – Track Only | ||
- | 0x10 – Search Only | ||
- | 0x11 – Invalid | ||
- | Search Mode: 0x27 – Bits 5, 6 Sets the Mode in which the search for the optimal phase is performed | ||
- | 0x00 – Down | ||
- | 0x01 – Up | ||
- | 0x10 – Up/Down (Optimal Setting) | ||
- | 0x11 – Invalid | ||
- | Search GB: sets a GB from the beginning and end of the Mu Delay line in which the Mu controller will not enter | ||
- | into unless it does not find a valid phase outside the GB. Register 0x29 bits 0-4. Optimal value is Decimal 11. | ||
- | Tolerance: Sets the Tolerance of the phase search. Register 0x29 bit 7 | ||
- | 0 – Not Exact. Can find a phase within 2 phases of the desired phase | ||
- | 1- Exact. Finds the exact phase you are targeting (Optimal Setting) | ||
- | ContRST: Controls whether the controller will reset or continue if it does not find the desired phase | ||
- | 0 – Continue (Optimal Setting) | ||
- | 1 – Reset | ||
- | Phase Detector Enable: Register 0x24 bit 5. Enables the Phase Detector (Set to 1 to enable the Phase Detector) | ||
- | Phase Detector Comparator Boost: Optimizes the bias to the Phase Detector (Set to 1 to enable) | ||
- | Bias: Register 0x24 Bits 0-3: Manual Control of the bias if the Boost control is not enabled | ||
- | Duty Cycle Fix: Register 0x25 Bit 7 Enables the duty cycle correction in the Mu Controller. Recommended to | ||
- | always enable (Set to 1 to enable) | ||
- | Direction: Register 0x25 Bit 6 Sets the direction that the duty cycle will be corrected | ||
- | 0 – Negative (Optimal Setting) | ||
- | 1 - Positive | ||
- | Offset: Register Register 0x25 Bit 0-5 Sets the Duty Cycle Correction manually if Fix is not enabled | ||
- | The status read back bits for the mu controller are as follows: | ||
- | MU_LCK: Register 0x2A bit 0 (value of 1 means the controller is locked) | ||
- | LST_LCK: Register 0x2A bit 1 (Value of 1 means the control lost lock) | ||
- | In order to read back the present MU Delay and phase value, it is necessary to set the Read bit high and then | ||
- | low before the values can be read back: | ||
- | Read: Register 0x26 Bit 3 | ||
- | Mu Delay Readback: Register 0x28 bits 0-7 and 0x27 bits 6,7 | ||
- | (Total of 9 bits in the read back the maximum Mu delay value is d432 or x1B0) | ||
- | MUD_PH_Readback: | ||
- | In order to use the Mu controller in manual mode the following bits are utilized: | ||
- | Mu Controller Enable: Register 0x26 Bit 0 (Set to 0 to disable the controller) | ||
- | MU_DEL_Manual: | ||
- | the maximum Mu delay value is d432 or x1B0) | ||
- | ==== LVDS Receiver Controls ==== | ||
- | RCV_LOOP - On (Register 0x10 bit 1 set to 1) | ||
- | RCV_ENA - On (Register 0x10 bit 0 set to 1) | ||
- | LCKTHR - 2 (Register 0x15 bits 0-4) | ||
- | RVCR_GAIN - 1 (Register 0x11 bit 0 set to 1) | ||
- | FINE_DELAY_MID - 7 (Register 0x11 bits 2-5) | ||
- | FINE_DELAY_SKEW - 2 (Register 0x13 bits 0-4) | ||
- | Sample_Delay: | ||
- | Register 0x12 Optimal value is 166 which is the center of the delay line. The maximum delay | ||
- | value is d333 or x14D. | ||
- | DCI_Delay: Must be equal to the Sample_delay. Register 0x13 bits 4-7 Register 0x14 bits 0-5. | ||
- | Optimal value is also 166 which is the center of the delay line. The maximum delay value is | ||
- | d333 or x14D. | ||
- | o ensure that the LVDS Controller is locked and tracking check the status of the following bits: | ||
- | RCVR Lock (Register 0x21 bit 0) This should be high if the controller is | ||
- | locked | ||
- | TRK_ON (Register 0x21 bit 3) This should be high if the controller is tracking |