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| resources:eval:dpg:ad9152-fmc-ebz [02 Aug 2022 12:42] – [Initial Set-Up] Shine Cabatan | resources:eval:dpg:ad9152-fmc-ebz [11 Oct 2022 14:05] (current) – [Software Needed] Shine Cabatan |
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| This user guide describes both the hardware and software setup needed to acquire data capture from [[adi>EVAL-AD9152|AD9152-FMC-EBZ]] evaluation board to characterize [[adi>AD9152]] 16-bit 2.25Gsps dual JESD204B signal processing RF Digital to Analog Converter. | This user guide describes both the hardware and software setup needed to acquire data capture from [[adi>EVAL-AD9152|AD9152-FMC-EBZ]] evaluation board to characterize [[adi>AD9152]] 16-bit 2.25Gsps dual JESD204B signal processing RF Digital to Analog Converter. |
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| The [[adi>EVAL-AD9152|AD9152-FMC-EBZ]] is an FMC mezzanine card and connects to an [[adi>eval-ads7-v2|ADS7-V2]] or [[adi>eval-ads8-v1ebz|ADS8-V1]] data pattern generator system. The ADS7-V2/ADS8-V1 automatically formats the data and sends it to the AD9152-FMC-EBZ via its JESD204B lanes. The AD9152-FMC-EBZ is an FMC mezzanine card. +12V, +3.3V, and VADJ power supply rails are provided by the ADS7-V2/ADS8-V1 system via the FMC connector P1. A clock distribution chip AD9516 is included on this EVB as a clock fan-out and frequency divider for the DACCLK, JESD204B SYSREF signals, and a GBTCLK clock used by the ADS7-V2/ADS8-V1. There is also an FMC standard I2C bus that is used by the ADS7-V2/ADS8-V1 to identify the AD9152-FMC-EBZ. This I2C interface is implemented in software in the AD9152-FMC-EBZ PIC processor (XU1). All ADS7-V2/ADS8-V1 to/from AD9152-FMC-EBZ interface signals are connected via the FMC connector P1. | The [[adi>EVAL-AD9152|AD9152-FMC-EBZ]] is an FMC mezzanine card and connects to an [[adi>eval-ads7-v2|ADS7-V2]] or [[adi>eval-ads8-v1ebz|ADS8-V1]] data pattern generator system. The ADS7-V2/ADS8-V1 automatically formats the data and sends it to the AD9152-FMC-EBZ via its JESD204B lanes. +12V, +3.3V, and VADJ power supply rails are provided by the ADS7-V2/ADS8-V1 system via the FMC connector P1. A clock distribution chip AD9516 is included on this EVB as a clock fan-out and frequency divider for the DACCLK, JESD204B SYSREF signals, and a GBTCLK clock used by the ADS7-V2/ADS8-V1. There is also an FMC standard I2C bus that is used by the ADS7-V2/ADS8-V1 to identify the AD9152-FMC-EBZ. This I2C interface is implemented in software in the AD9152-FMC-EBZ PIC processor (XU1). All ADS7-V2/ADS8-V1 to/from AD9152-FMC-EBZ interface signals are connected via the FMC connector P1. |
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| ===== Typical Setup ===== | ===== Typical Setup ===== |
| <WRAP centeralign> {{ :resources:eval:dpg:ad9152-fmc-ebz_setup_with_labels.jpg?600 |}}//Figure 1a. AD9152-FMC-EBZ Setup with ADS7-V2EBZ//</WRAP> | <WRAP centeralign> {{ :resources:eval:dpg:ad9152-fmc-ebz_setup_with_labels.jpg?600 |}}//Figure 1a. AD9152-FMC-EBZ Setup with ADS7-V2EBZ//</WRAP> |
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| <WRAP centeralign> {{ :resources:eval:dpg:ad9152-fmc-ebz_setup_with_labels.jpg?600 |}}//Figure 1b. AD9152-FMC-EBZ Setup with ADS8-V1EBZ//</WRAP> | <WRAP centeralign> {{ :resources:eval:dpg:ad9152-fmc-ebz_setup2_with_labels.jpg?600 |}}//Figure 1b. AD9152-FMC-EBZ Setup with ADS8-V1EBZ//</WRAP> |
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| <note tip>Tip: Click on any picture in this guide to open an enlarged version.</note> | <note tip>Tip: Click on any picture in this guide to open an enlarged version.</note> |
| * [[:resources:eval:dpg:ad9152-ebz|AD9152-EBZ]] | * [[:resources:eval:dpg:ad9152-ebz|AD9152-EBZ]] |
| * [[:resources:eval:dpg:ad9152-adrf6720-ebz|AD9152-ADRF6720-EBZ]] | * [[:resources:eval:dpg:ad9152-adrf6720-ebz|AD9152-ADRF6720-EBZ]] |
| | * [[:resources:eval:dpg:ads7|ADS7-V1/-V2 for High-Speed DAC Evaluation]] |
| * Datasheet: [[adi>media/en/technical-documentation/data-sheets/AD9152.pdf|AD9152]] | * Datasheet: [[adi>media/en/technical-documentation/data-sheets/AD9152.pdf|AD9152]] |
| * IBIS Model: [[ibis>ad9152bcpz|AD9152]] | * IBIS Model: [[ibis>ad9152bcpz|AD9152]] |
| * [[adi>plugins/ace/board.ad9152.1.2020.4400.acezip|AD9152 ACE Plugin]] | * [[adi>plugins/ace/board.ad9152.1.2020.4400.acezip|AD9152 ACE Plugin]] |
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| <note important>**Known Issue:** ACE may fail to detect HS-DAC boards, details [[resources:tools-software:ace:knownissues#high-speed_dac_eval_boards_are_not_discovered|here]].</note> | <note important> |
| | * Do not install ACE on a computer with DAC Software Suite. |
| | * **Known Issue:** ACE may fail to detect HS-DAC boards, details [[resources:tools-software:ace:knownissues#high-speed_dac_eval_boards_are_not_discovered|here]]. |
| | </note> |
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| ===== Hardware Needed ===== | ===== Hardware Needed ===== |
| ===== Quick Start Guide ===== | ===== Quick Start Guide ===== |
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| - Attach AD9152-FMC-EBZ onto the FMC connector of ADS7-V2 or ADS8-V1 controller board. Connect the evaluation board to PC via USB, the continuous waveform generator output to J1, and one of the DAC outputs to a signal/spectrum analyzer. Connect ADS7-V2/ADS8-V1 to PC via USB and to a 12V 60W AC/DC power supply, then switch the board ON using S1 beside the connector for 12V supply. Refer to [[:resources:eval:dpg:ad9152-fmc-ebz|Typical Setup]] section for pictures of actual evaluation setup. | - Attach AD9152-FMC-EBZ onto the FMC connector of ADS7-V2 or ADS8-V1 controller board. Connect the evaluation board to PC via USB, the continuous waveform generator output to J1, and one of the DAC outputs (J4 or J17) to a signal/spectrum analyzer. Connect ADS7-V2/ADS8-V1 to PC via USB and to a 12V 60W AC/DC power supply, then switch the board ON using S1 beside the connector for 12V supply. Refer to [[:resources:eval:dpg:ad9152-fmc-ebz#typical setup|Typical Setup]] section for pictures of actual evaluation setup. |
| - Set the frequency of the continuous waveform generator output to **1.5 GHz** and the output level to **+3 dBm**. Enable the output. <WRAP centeralign>{{ :resources:eval:dpg:ad9152-fmc-ebz_dpg_board_detect.png?600 |}}//Figure 2. ADS7-V2 and AD9152 detected in DPG Software//</WRAP> | - Set the frequency of the continuous waveform generator output to **1.5 GHz** and the output level to **+3 dBm**. Enable the output. <WRAP centeralign>{{ :resources:eval:dpg:ad9152-fmc-ebz_dpg_board_detect_ads7.png?600 |}}//Figure 2. ADS7-V2 and AD9152 detected in DPG Software//</WRAP> |
| - Start DPG Lite or DPG Downloader. A panel named after the detected controller board should appear at the bottom of the DPG window. The device on the evaluation board and the data interface should also be automatically detected by the software and shown at **Evaluation Board** and **Port Configuration**, respectively. See Figure 2. <WRAP centeralign>{{ :resources:eval:dpg:ad9152-fmc-ebz_ace_board_detect.png?600 |}}//Figure 3. AD9152-FMC-EBZ detected in ACE//</WRAP> | - Start DPG Lite or DPG Downloader. A panel named after the detected controller board should appear at the bottom of the DPG window. The device on the evaluation board and the data interface should also be automatically detected by the software and shown at **Evaluation Board** and **Port Configuration**, respectively. See Figure 2. <WRAP centeralign>{{ :resources:eval:dpg:ad9152-fmc-ebz_ace_board_detect_ads7.png?600 |}}//Figure 3. AD9152-FMC-EBZ detected in ACE//</WRAP> |
| - Open ACE. The board will automatically be recognized by the software as shown in Figure 3. Otherwise, install the plugin for AD9152 evaluation board by following the steps in this page: [[:resources:tools-software:ace:userguide:quickstart|Quickstart - ACE Quickstart and Plug-in Installation]]. <WRAP centeralign>{{ :resources:eval:dpg:ad9152-fmc-ebz_ace_configuration_settings.png?600 |}}//Figure 4. ACE Initial Configuration Wizard//</WRAP> | - Open ACE. The board will automatically be recognized by the software as shown in Figure 3. Otherwise, install the plugin for AD9152 evaluation board by following the steps in this page: [[:resources:tools-software:ace:userguide:quickstart|Quickstart - ACE Quickstart and Plug-in Installation]]. <WRAP centeralign>{{ :resources:eval:dpg:ad9152-fmc-ebz_ace_configuration_wizard_ads7.png?600 |}}//Figure 4. ACE Initial Configuration Wizard//</WRAP><WRAP centeralign>{{ :resources:eval:dpg:ad9152-fmc-ebz_ace_chipview_ads7.png?600 |}}//Figure 5. ACE AD9152 Chipview Tab//</WRAP> |
| - In ACE, apply the configuration wizard settings enumerated below and shown in Figure 4. JESD204B PLL should lock and the indicator should turn green. | - In ACE, apply the configuration wizard settings enumerated below and shown in Figure 4. JESD204B PLL should lock and the indicator should turn green. |
| * **FDAC:** 1.5 GHz | * **FDAC:** 1.5 GHz |
| * **DigGain:** True | * **DigGain:** True |
| * **PLL_Enable:** False | * **PLL_Enable:** False |
| * **Input Data Format:** 2's complement <WRAP centeralign>{{ :resources:eval:dpg:ad9152-fmc-ebz_dpg_generate_output.png?600 |}}//Figure 5. Single Tone and ADS7-V2 Configuration Panels in DPG//</WRAP> | * **Input Data Format:** 2's complement <WRAP centeralign>{{ :resources:eval:dpg:ad9152-fmc-ebz_dpg_generate_output.png?600 |}}//Figure 6. Single Tone and ADS7-V2 Configuration Panels in DPG//</WRAP> |
| - In DPG Lite or DPG Downloader, configure single tone waveform generation. From the **Add Generator Waveforms** pulldown menu, select **Single Tone**. Apply the following settings: | - In DPG Lite or DPG Downloader, configure single tone waveform generation. From the **Add Generator Waveforms** pulldown menu, select **Single Tone**. Apply the following settings: |
| * **Data Rate:** 350 MHz | * **Data Rate:** 350 MHz |
| * **Unsigned Data:** unchecked | * **Unsigned Data:** unchecked |
| * **Generate Complex Data (I & Q):** checked | * **Generate Complex Data (I & Q):** checked |
| - In the ADS7-V2 or ADS8-V1 panel in the DPG window, configure **Data Playback** by selecting tones for the DAC outputs from each dropdown menu. Set **JESD Mode** to Mode 4, **Links** to Single and **Subclass** to 1.<WRAP centeralign>{{ :resources:eval:dpg:ad9152:ad9152-fmc_dac_output.png |}}//Figure 6. AD9152 IDAC Output FFT for Data Rate = 350 MHz, FOUT = 100 MHz//</WRAP> | - In the ADS7-V2 or ADS8-V1 panel in the DPG window, configure **Data Playback** by selecting tones for the DAC outputs from each dropdown menu. Set **JESD Mode** to Mode 4, **Links** to Single and **Subclass** to 1.<WRAP centeralign>{{ :resources:eval:dpg:ad9152:ad9152-fmc_dac_output.png |}}//Figure 7. AD9152 DAC Output FFT for Data Rate = 350 MHz, FOUT = 100 MHz//</WRAP> |
| - Press the download arrow ({{:resources:eval:dpg:9154_down_arrow.png}}) then the play button ({{:resources:eval:dpg:9154_right_green_arrow.png}}). **Serial Line Rate** should appear as 3.75 Gbps and **Sync Status** should have a check mark. FFT plot of IDAC output is in Figure 6. | - Press the download arrow ({{:resources:eval:dpg:9154_down_arrow.png}}) then the play button ({{:resources:eval:dpg:9154_right_green_arrow.png}}). As in Figure 6, **Serial Line Rate** should appear as 3.75 Gbps and **Sync Status** should have a check mark. FFT plot of the DAC output is in Figure 7. |
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| ===== Hardware Setup ===== | |
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| A low phase noise high frequency clock source should be connected to the SMA connector J1, This is the DACCLK input. The spectrum analyzer should be connected to the SMA connector,J4 or J17. The evaluation board connects to the ADS7 through the connectors P3. The PC should be connected to the EVB using the mini-USB connector XP2 after installation of the Evaluation Board software. Figure 1 shows the block diagram of the set-up. | |
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