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| resources:eval:dpg:ad9142a-m5375-ebz [16 Jun 2017 16:03] – Bailey Meyer | resources:eval:dpg:ad9142a-m5375-ebz [22 Jun 2022 03:14] (current) – Draft Deferson Romero | ||
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| - | ====== AD9142A-M5375-EBZ Evaluation Board Quick Start Guide ====== | + | ======EVALUATING THE AD9142A |
| - | ===== Getting Started with the AD9142A-M5375-EBZ Evaluation Board and Software | + | =====Preface===== |
| - | ==== What's in the Box ==== | + | This user guide describes both the hardware |
| - | * AD9142A-M5375-EBZ | + | |
| - | * Evaluation Board CD | + | |
| - | * Mini-USB Cable | + | |
| - | ==== Recommended Equipment List ==== | + | |
| - | * +5Vdc, Power Supply | + | |
| - | * 2 Sinusoidal Clock Sources | + | |
| - | * Spectrum Analyzer | + | |
| - | * Data Pattern Generator Series 2 or 3 (DPG) | + | |
| - | ==== Introduction ==== | + | |
| - | The AD9142A-M5375-EBZ connects to a DPG for quick evaluation of the AD9142A, a high-speed, signal processing Digital to Analog Converter. The DPG automatically formats the data and sends it to the AD9142A-M5375-EBZ, | + | |
| - | ===== AD9142A Evaluation Software ===== | + | |
| - | The AD9142A Evaluation Board software | + | |
| - | ===== Hardware Setup ===== | + | |
| - | Connect +5.0V to P5, GND to P6. One low phase noise high frequency clock source should be connected to the SMA connector, J1 (AD9516_CLKIN). The other low phase noise high frequency clock source should be connected to the SMA connector, J15 (LO_IN), and the spectrum analyzer should be connected | + | |
| - | <WRAP center> | + | |
| - | | {{ : | + | =====Typical Setup===== |
| - | | | + | <WRAP centeralign> |
| - | </ | + | <WRAP centeralign> |
| - | ===== Getting Started ===== | + | <note tip>Tip: Click on any picture |
| - | The PC software comes on the included Evaluation Board CD, but may also be downloaded from the DPG Web site at http:// | + | |
| - | ==== ACE ==== | + | |
| - | === Initial Set-Up === | + | |
| - | 1. Install the DPG Downloader and ACE software and support files on your PC. Follow the instructions | + | |
| - | 2. Use a USB cable to connect the EVB to your PC and connect the lab equipment to the EVB. \\ \\ | + | |
| - | 3. Connect the DPG unit to your PC and turn on the unit. \\ \\ | + | |
| - | === Single-Tone Test === | + | |
| - | These settings configure the AD9142A to output a sine wave using the DPG and ACE and allow the user to view the single-tone performance at the IQMOD output, under the condition: Fdata = 350MHz, 4X interpolation, | + | |
| - | 1. To begin, | + | |
| - | If the board is connected properly, | + | =====Helpful Files: |
| + | * [[: | ||
| + | * Datasheet: [[adi> | ||
| + | * IBIS Model: [[adi> | ||
| + | * Schematics: {{ : | ||
| + | * Bill of Materials: {{ : | ||
| + | * PCB Gerber Files: {{ : | ||
| + | * PCB Board Files: {{ : | ||
| + | * PCB Layout: {{ : | ||
| + | =====Software Needed: | ||
| + | * [[: | ||
| + | * [[: | ||
| + | <note important> | ||
| + | |||
| + | =====Hardware | ||
| + | * [[adi>en/design-center/evaluation-hardware-and-software/ | ||
| + | * [[: | ||
| + | * [[adi> | ||
| + | * PC with ACE and DPG Lite Software Applications | ||
| + | * 5Vdc Power Supply | ||
| + | * (2) Banana Plug Cables | ||
| + | * High-Frequency Continuous Wave Generator | ||
| + | * Signal/ | ||
| + | * USB-A to USB-Mini Cable | ||
| + | * (2) SMA Cables | ||
| + | * The following are included in SDP-H1 Evaluation Kit: | ||
| + | * 12Vdc Wall Adapter | ||
| + | * USB-A to USB-Mini Cable | ||
| + | * The following are included in ADS7-V2 Evaluation Kit: | ||
| + | * 12Vdc Power Supply | ||
| + | * Power Cord | ||
| + | * USB-A to USB-B Cable | ||
| - | < | + | =====Quick Start Guide===== |
| - | | {{ : | + | ====Jumpers for Selecting the DAC Output==== |
| - | | Figure | + | Jumpers JP4, JP5, JP6, and JP7 select the output configuration. By default, the DAC output connected to the LPF and the ADL537x analog quadrature modulator. For selecting DAC output configuration, |
| - | </ | + | <WRAP >//Table 1. Jumper Configurations for Viewing DAC Output and Modulator Output//</ |
| + | ^Output Viewed ^SMA Output ^Jumper Configuration^ | ||
| + | |DAC Output|J3 (DAC1_Output) or J4 (DAC2_Output)|JP4 and JP5 Pin 2 to Pin 3 (outer pads), JP6 and JP7 Pin 2 to Pin 3 (outer pads)| | ||
| + | |Modulator Output (Default)|J6 (MOD_OUT)|JP4 and JP5 Pin 1 to Pin 2 (inner pads), JP6 and JP7 Pin 1 to Pin 2 (inner pads)| | ||
| - | Ensure that the {{: | + | |{{: |
| + | | DAC Output Configuration | ||
| + | <WRAP centeralign>// | ||
| + | ====Jumper for Selecting Clock Configuration==== | ||
| + | The AD9142A-M5372-EBZ / AD9142A-M5375-EBZ evaluates both the DAC outputs as well as the AQM outputs. Refer to Table 3 for clock configuration. | ||
| + | <WRAP >//Table 3. Clock Configuration//</ | ||
| + | ^Output Viewed ^Clock Input ^Local Oscillator Input^ | ||
| + | |DAC Output|J1 (CLKIN)| | | ||
| + | |Modulator Output (Default)|J1 (CLKIN)|J15 (LO_IN)| | ||
| + | ====Evaluation Guide==== | ||
| + | - Make sure that on AD9142A-M5375-EBZ, | ||
| + | - Follow evaluation setup in Figure 1a and 1b. | ||
| + | * Attach | ||
| + | * Connect continuous wave generator for clock input to J1 (AD9516 CLK_IN). | ||
| + | * Connect | ||
| + | * Connect | ||
| + | * Connect SDP-H1/ | ||
| + | * Set clock input / continuous wave generator to **500MHz** and **2dBm**. | ||
| + | - Open ACE. The board will automatically be recognized by the software. Otherwise, install the plugin for AD9142A-M5375-EBZ evaluation board. Double | ||
| + | - Open the DPGDownloaderLite. The evaluation board, controller board and DCO Frequency of around **250MHz** will be automatically recognized by DPG. | ||
| + | - In DPGDownloaderLite, | ||
| + | - Select the in-phase tone from the **I Data Vector** pulldown menu and the quadrature tone from the **Q Data Vector** pulldown menu.< | ||
| + | - Press the download arrow and then the play button. The spectrum similar to Figure 8 should appear in the signal/ | ||
| - | <WRAP center> | ||
| - | | {{ : | ||
| - | | Figure 4. The AD9142A-M537x system. | ||
| - | </ | ||
| - | |||
| - | 2. Configure the hardware according to the hardware set-up instructions given in the Hardware Setup section above. Set the frequency of the DAC clock signal generator to 1400MHz, and the output level to 6dBm. The spectrum analyzer can be configured with Center Frequency = 2050 MHz, Span = 200 MHz, and Resolution Bandwidth of 30 kHz. Choose Input Attenuation to be 24dB. This can be adjusted later if indications are that the analyzer is causing degradations. \\ \\ | ||
| - | 3. Follow the sequence below to configure the AD9142A using ACE. \\ \\ | ||
| - | a. Click " | ||
| - | |||
| - | <WRAP column 40%> | ||
| - | | {{ : | ||
| - | </ | ||
| - | <WRAP column 55%> | ||
| - | | {{ : | ||
| - | </ | ||
| - | <WRAP clear> | ||
| - | </ | ||
| - | <WRAP column 40%> | ||
| - | <WRAP centeralign> | ||
| - | </ | ||
| - | <WRAP column 55%> | ||
| - | <WRAP centeralign> | ||
| - | </ | ||
| - | <WRAP clear> | ||
| - | </ | ||
| - | |||
| - | b. Double click on the AD9142A component on the board diagram. This brings up the chip diagram. Set all the settings to match those in the chip diagram below, and click "Apply Changes." | ||
| - | |||
| - | <WRAP center> | ||
| - | | {{ : | ||
| - | | Figure 7. Chip block diagram of the AD9142A. | ||
| - | </ | ||
| - | |||
| - | c. Open DPGDownloader. (Start > All Programs > Analog Devices > DPG > DPGDownloader). Ensure that the program detects the AD9142A, as indicated in the " | ||
| - | |||
| - | <WRAP center> | ||
| - | | {{ : | ||
| - | | Figure 8. | | ||
| - | </ | ||
| - | |||
| - | d. Click on "Add Generated Waveform," | ||
| - | e. Click Download ({{: | ||
| - | 4. The current on the 5V supply should read about 1280mA. \\ | ||
| - | |||
| - | <WRAP center> | ||
| - | | {{ : | ||
| - | | Figure 9. AD9142A-M5375 Eval Board output Spectrum | ||
| - | </ | ||
| - | ==== SPI Software ==== | ||
| - | === Initial Set-Up === | ||
| - | 1. Install the DPG Downloader and AD9142A SPI software and support files on your PC. Follow the instructions in the installation wizard and use the default (recommended) installation settings. \\ \\ | ||
| - | 2. Use a USB cable to connect the EVB to your PC and connect the lab equipment to the EVB. \\ \\ | ||
| - | 3. Connect the DGP2 unit to your PC and turn on the unit. \\ \\ | ||
| - | === Single-Tone Test === | ||
| - | These settings configure the AD9142A to output a sine wave using the DPG and allow the user to view the single-tone performance at the IQMOD output, under the condition: Fdata = 350MHz, 4X interpolation, | ||
| - | 1. To begin, open the AD9142A SPI application (Start > All Programs > Analog Devices > AD9142A > AD9142A SPI). The screen should look similar to Figure 10. \\ \\ | ||
| - | <WRAP center> | ||
| - | |||
| - | | {{: | ||
| - | | Figure 10. Entry Screen of the AD9142A SPI software | ||
| - | </ | ||
| - | |||
| - | 2. Configure the hardware according to the hardware set-up instructions given in the Hardware Setup section above. Set the frequency of the DAC clock signal generator to 1400MHz, and the output level to 6dBm. The spectrum analyzer can be configured with Center Frequency = 2000 MHz, Span = 200 MHz, and Resolution Bandwidth of 30 kHz. Choose Input Attenuation to be 24dB. This can be adjusted later if indications are that the analyzer is causing degradations. \\ \\ | ||
| - | 3. Follow the sequence below to configure the AD9142A SPI registers. \\ \\ | ||
| - | a. Click “Reset DAC” button on the “Quick Start” tab. \\ \\ | ||
| - | b. Click “Restore Registers from File” and select the configuration file “Config_4X.csv”. | ||
| - | c. Click “AD9516 Update” button. This step updates the clock distribution chip AD9516 with the settings that were loaded from the configuration file. \\ \\ | ||
| - | d. There may be a few registers highlighted in red. The red highlights mean mismatches between the SPI read and write values in the software. Clicking “Read All Registers” reads back all the current values in the registers, which should resolve the highlights. \\ \\ | ||
| - | e. Toggle register “FIFO SPI RESET REQUEST”. The FIFO level readback registers (INTEGRAL and FRACTIOANAL) should now match the FIFO level request registers. \\ \\ | ||
| - | f. Open DPG Downloader if you have not done so. (Start > All Programs > Analog Devices > DPG > DPGDownloader). Ensure that the program detects the AD9142A, as indicated in the “Evaluation Board” drop-down list, and select it. For this evaluation board, LVDS is the only valid Port Configuration, | ||
| - | <WRAP center> | ||
| - | |||
| - | | {{ : | ||
| - | | Figure 11. DPG Downloader Panel | | ||
| - | </ | ||
| - | |||
| - | g. Click on “Add Generated Waveform”, | ||
| - | |||
| - | <WRAP center> | ||
| - | |||
| - | | {{ : | ||
| - | | Figure 12. DPG Downloader sinewave vector | ||
| - | </ | ||
| - | |||
| - | h. Click Download ({{: | ||
| - | i. Go back to the AD9142A SPI software and toggle the “FIFO SPI RESET REQUEST” button (from 0 to 1 and back to 0) to reset the FIFO. The FIFO level readback registers (INTEGRAL and FRACTIOANAL) should now match the FIFO level request registers. The AD9142A SPI software and the spectrum analyzer should look like Figure 13 and Figure 14 respectively. \\ \\ | ||
| - | |||
| - | <WRAP center> | ||
| - | |||
| - | | {{ : | ||
| - | | Figure 13. Configured Quick Start Tab of the AD9142A SPI software | ||
| - | </ | ||
| - | |||
| - | 4. The current on the 5V supply should read about 1280mA. \\ | ||
| - | |||
| - | <WRAP center> | ||
| - | | {{ : | ||
| - | | Figure 14. AD9142A-M5375 Eval Board output Spectrum | ||
| - | </ | ||
| - | ===== SPI SOFTWARE ===== | ||
| - | The AD9142A SPI software is conveniently organized in a series of tabs that groups registers according to their functions. In this way, all registers associated with the digital functions, for example, are on the “Digital Functions” tab. All registers associated with the PLL are on the “PLL” tab, and so on. Normally the “Quick Start” tab is sufficient for a quick evaluation. The most frequently used register controls are included on this tab. A full description of each register and its settings is given in the AD9142A data sheet. Some of the registers and their functions are described here as they pertain to the AD9142A evaluation board. Please note that some of the screen images in this document may not match exactly with the latest revision of the software, due to ongoing improvements and enhancements to the software. \\ | ||
| - | The full screen layout is shown in Figure 5. The tabs can be seen across the top of the work area, and four function buttons in the menu area. “Save Registers to File” and “Restore Registers from File” allow the user to save the current register settings into a file for later uses. A register is immediately updated when the value in the control is changed. Switching between tabs does not update register values. “Read All Registers” can be used to monitor a resister with changing readback values. “ Record Sequence” allows the user to record a series of SPI writes in a particular order and to play back the sequence later. A short description of the register is shown in the status bar on the bottom of the work area when the mouse curser hovers over the control. Some of the tabs are discussed below. | ||
| - | ==== Quick Start ==== | ||
| - | The “Quick Start” tab has selections that apply to the general configuration of the DAC. Reset DAC is recommended every time when the DAC is powered on or reset. Interpolation Rate allows the user to select among the 3 interpolation modes (2X, 4X, and 8X). When the NCO is used, set NCO Enable to 1, fill in the NCO frequency tuning word with the desired value and toggle SPI Update Request. To use the Fs/4 modulation, turn on the Fs/4 Modulation control. FIFO SPI Reset Request sets the FIFO with the requested value through a SPI command. The FIFO Level Read Back should reflect the actual FIFO level after the FIFO SPI Reset Request. Note loading/ | ||
| - | |||
| - | <WRAP center> | ||
| - | | {{ : | ||
| - | | Figure 15. AD9142A SPI Quick Start tab | | ||
| - | </ | ||
| - | ==== PLL ==== | ||
| - | The “PLL” tab includes all the PLL control registers. The recommended settings for the best performance is PLL Charge Pump Current = 7 and PLL LOOP BW = 7. The user needs to follow the sequence below to enable the PLL. | ||
| - | 1. Choose the desired divide ratios in the Loop Divider and the VCO Divider. \\ | ||
| - | 2. Set PLL Charge Pump Current and PLL Loop BW settings to 7. \\ | ||
| - | 3. Set the PLL Mode to Manual. \\ | ||
| - | 4. Turn on PLL Enable. \\ | ||
| - | 5. Set the PLL Mode to Auto. \\ | ||
| - | |||
| - | <WRAP center> | ||
| - | | {{ : | ||
| - | | Figure 16. AD9142A SPI PLL Tab | | ||
| - | </ | ||
| - | ===== EVB Jumper Configurations ===== | ||
| - | This evaluation board allows evaluation of both the DAC IF outputs as well as the modulator RF outputs. | ||
| - | |||
| - | <WRAP center> | ||
| - | ^ Output Viewed ^ SMA Connector ^ Jumper Configurations^ | ||
| - | | I DAC Output | ||
| - | | Q DAC Output | ||
| - | | ADL5375 RF Output | ||
| - | </ | ||
| - | |||
| - | Note: When viewing the modulator output, a local oscillator (LO) must be connected to J15 (”LO_IN”) to properly modulate the signals | ||
| - | ===== ACE Software ===== | ||
| - | The ACE software is organized to allow the user to evaluate and control the AD9122A evaluation board. The “Initial Configuration” wizard, which is only available for certain boards, controls the DAC and PLL setups. Block diagram views of the board and chip contain elements that can be used to vary parameters like ref current and data format. These parameters can be changed using check boxes, drop down menus, and input boxes. Some parameters do not have settings shown in the diagram. Double click on the parameter to view the available settings, seen with the NCO settings below. | ||
| - | |||
| - | {{ : | ||
| - | <WRAP clear> | ||
| - | </ | ||
| - | <WRAP centeralign> | ||
| - | |||
| - | In addition, some parameters can be enabled or disabled. This feature is evident by the color of the block parameter. For example, if the block parameter is dark blue, the parameter is enabled. If it is light grey, it is disabled. To enable or disable a parameter, click on it. | ||
| - | |||
| - | <WRAP column 40%> | ||
| - | | {{ : | ||
| - | </ | ||
| - | <WRAP column 55%> | ||
| - | | {{ : | ||
| - | </ | ||
| - | <WRAP clear> | ||
| - | </ | ||
| - | <WRAP column 40%> | ||
| - | <WRAP centeralign> | ||
| - | </ | ||
| - | <WRAP column 55%> | ||
| - | <WRAP centeralign> | ||
| - | </ | ||
| - | <WRAP clear> | ||
| - | </ | ||
| - | |||
| - | More direct changes to registers and bit fields can be made in the memory map, which is linked from the chip block diagram through the “Proceed to Memory Map” button. In this view, names, addresses, and data can be manually altered by the user. | ||
| - | |||
| - | | {{ : | ||
| - | <WRAP clear> | ||
| - | </ | ||
| - | <WRAP centeralign> | ||
| - | |||
| - | ACE also contains the Macro Tool, which can be used to record register reads and writes. This is executed in the memory map view or with the initialization wizard. To use, check the “Record Sub-Commands” checkbox and press the record button. Changes in the memory map, which are bolded until they are applied to the part, are recorded as UI commands by the macro tool once the changes are made. Changed register write commands for the controls are also recorded. Hit “Apply Changes” to execute the commands and make changes in the memory map. To stop recording, click the “Stop Recording” button. A macro tool page with the command steps will be created. The macro can be saved using the “Save Macro” button so that it may be loaded for future use. | ||
| - | |||
| - | | {{ : | ||
| - | <WRAP clear> | ||
| - | </ | ||
| - | <WRAP centeralign> | ||
| - | |||
| - | The raw macro file will be saved using ACE syntax, which is not easily readable. To remedy this, the ACE software download includes the Macro to Hex Conversion Tool. The user can choose to include or exclude register write, reads, and/or comments in the conversion. The file pathways for the source and save paths should be the same, except that one should be an .acemacro file and the other should be a .txt file. The “Convert” button converts and opens the converted text file, which is easier to read. The conversion tool can also convert back to an .acemacro file if desired. | ||
| - | |||
| - | <WRAP column 40%> | ||
| - | | {{ : | ||
| - | </ | ||
| - | <WRAP column 55%> | ||
| - | | {{ : | ||
| - | </ | ||
| - | <WRAP clear> | ||
| - | </ | ||
| - | <WRAP column 40%> | ||
| - | <WRAP centeralign> | ||
| - | </ | ||
| - | <WRAP column 55%> | ||
| - | <WRAP centeralign> | ||
| - | </ | ||
| - | <WRAP clear> | ||
| - | </ | ||
| - | For more information about ACE and its features, visit https:// | ||
resources/eval/dpg/ad9142a-m5375-ebz.txt · Last modified: 22 Jun 2022 03:14 by Deferson Romero