Wiki

Analog Devices Wiki

English
English
简体中文
简体中文
日本語
日本語
Руccкий
Руccкий

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
resources:eval:dpg:ad9122-ebz [22 Jun 2022 03:08] – Draft Deferson Romeroresources:eval:dpg:ad9122-ebz [23 Jan 2024 07:33] (current) – Minor typo error: JP7 changed to JP17 John Marco Mina
Line 48: Line 48:
 <WRAP >//Table 1. Jumper Configurations for Viewing DAC Output and Modulator Output//</WRAP>  <WRAP >//Table 1. Jumper Configurations for Viewing DAC Output and Modulator Output//</WRAP> 
 ^Output Viewed ^SMA Output ^Jumper Configuration^ ^Output Viewed ^SMA Output ^Jumper Configuration^
-|DAC Output|J3 (DAC1_P) or J8 (DAC2_P)|JP4 and JP5 Pin 2 to Pin 3 (outer pads), JP6 and JP7 Pin 2 to Pin 3 (outer pads)| +|DAC Output|J3 (DAC1_P) or J8 (DAC2_P)|JP4 and JP5 Pin 2 to Pin 3 (outer pads), JP6 and JP17 Pin 2 to Pin 3 (outer pads)| 
-|Modulator Output (Default)|J6 (MOD_OUT)|JP4 and JP5 Pin 1 to Pin 2 (inner pads), JP6 and JP7 Pin 1 to Pin 2 (inner pads)|+|Modulator Output (Default)|J6 (MOD_OUT)|JP4 and JP5 Pin 1 to Pin 2 (inner pads), JP6 and JP17 Pin 1 to Pin 2 (inner pads)|
  
 |{{:resources:eval:dpg:ad9122_dac_output_config.png? }}|{{ :resources:eval:dpg:ad9122_modulator_output_config.png?|}}| |{{:resources:eval:dpg:ad9122_dac_output_config.png? }}|{{ :resources:eval:dpg:ad9122_modulator_output_config.png?|}}|
Line 77: Line 77:
 ^Output Viewed ^Clock Input ^Local Oscillator Input^ ^Output Viewed ^Clock Input ^Local Oscillator Input^
 |DAC Output|J1 (CLKIN)| | |DAC Output|J1 (CLKIN)| |
-|Modulator Output (Default)|J1 (CLKIN)|J15 (LO_IN)| +|Modulator Output (Default)|J1 (CLKIN)|J9 (LO_IN)| 
-The modulator LO input can be sourced through SMA connector J15 (LO_IN) with clock level at **3dBm**.+The modulator LO input can be sourced through SMA connector J9 (LO_IN) with clock level at **3dBm**.
 ====Evaluation Guide==== ====Evaluation Guide====
   - Make sure that on AD9121-M5375-EBZ/AD9122-M5375-EBZ/AD9125-M5375-EBZ, JP4, JP5, JP6, and JP17 are configured such that DAC output are connected with  J3 (DAC1_P) or J8 (DAC2_P). Refer to Figure 2.   - Make sure that on AD9121-M5375-EBZ/AD9122-M5375-EBZ/AD9125-M5375-EBZ, JP4, JP5, JP6, and JP17 are configured such that DAC output are connected with  J3 (DAC1_P) or J8 (DAC2_P). Refer to Figure 2.
resources/eval/dpg/ad9122-ebz.txt · Last modified: 23 Jan 2024 07:33 by John Marco Mina

Page Tools