This version (25 Apr 2022 04:11) was approved by John Xavier Toledo.The Previously approved version (21 Nov 2016 15:24) is available.Diff



This user guide describes the AD9652 evaluation board, AD9652-310EBZ, which provides all of the support circuitry required to operate this part in its various modes and configurations. The application software used to interface with the devices is also described.

The AD9652 data sheet provides additional information and should be consulted when using the evaluation board. All documents and software tools are available at For additional information or questions, send an email to

Typical Measurement Setup

Figure 1. Evaluation Board Connection—AD9652-310EBZ (on Left) and


  • Full featured evaluation board for the AD9652
  • SPI interface for setup and control
  • Balun/transformer or amplifier input drive option
  • On-board LDO regulator needing a single external 6 V, 2 A dc supply
  • VisualAnalog® and SPI controller software interfaces

Helpful Documents

Software Needed

Design and Integration Files



Equipment Needed

  • Analog signal source and antialiasing filter
  • Sample clock source
  • 2 switching power supplies (6.0 V, 2.5 A), CUI EPS060250UH-PHP-SZ provided
  • PC running Windows®
  • USB 2.0 port
  • HSC-ADC-EVALCZ FPGA-based data capture kit

Getting Started

This section provides quick start procedures for using the AD9652-310EBZ board. Both the default and optional settings are described.

Configuring the Board

Before using the software for testing, configure the evaluation board as follows:

  1. Connect the evaluation board to the data capture board, as shown in Figure 1.
  2. Connect one 6 V, 2.5 A switching power supply to the HSC-ADC-EVALCZ board.
  3. Connect the HSC-ADC-EVALCZ board to the PC with a USB cable. (Connect to J6)
  4. On the ADC evaluation board, verify the following jumpers below:
    • Place Power supply jumpers: P5, P9, and P13
    • Disable Amp: P16 and P31, jumper pins 1 and 2
    • P15 jumper pins 2 and 3
    • JP3 jumper should be installed
  5. Connect one 6 V, 2.5 A switching power supply to the AD9652-310EBZ board.
  6. On the ADC evaluation board, provide a clean, low jitter clock source to connector J6 at the desired ADC conversion rate. Note: The AD9652 has an input clock divider circuit which allows generators to drive a higher frequency clock, for this case apply the high frequency clock to J6 and program the proper divide using SPIController when it is used in a later step. The input clock level should be between 10dBm to 16dBm.
    • For the AD9652 evaluation board number 12048 RevC, the Clock Duty Cycle stabilizer should be disabled when using an input clock abouve 620 MHz.

Using the Software for Testing

Setting up the ADC Data Capture

After configuring the board, set up the ADC data capture using the following steps:

  1. Open VisualAnalog on the connected PC. The appropriate part type should be listed in the status bar of the VisualAnalog – New Canvas window. Select the template that corresponds to the type of testing to be performed (see Figure 2, where the AD9652 is shown as example).

    Figure 2. VisualAnalog, New Canvas Window

  2. After the template is selected, a message appears asking if the default configuration can be used to program the FPGA (Figure 3). Click YES and the window closes.

    Figure 3. VisualAnalog Default Configuration Message

  3. To change features to settings other than the default settings, click the Expand Display button, located on the bottom right corner of the window, to see what is shown in Figure 5. Detailed instructions for changing the features and capture settings can be found in the AN-905 Application Note, VisualAnalog Converter Evaluation Tool Version 1.0 User Manual. After the changes are made to the capture settings, click the Collapse Display button (see Figure 4).

Figure 4. VisualAnalog Window Toolbar, Collapsed Display

Figure 5. VisualAnalog, Main Window Expanded Display

Evaluation and Test

Setting up the SPI Controller Software

After the ADC data capture board setup is complete, set up the SPI controller software using the following procedure:

  1. Open the SPI controller software by going to the Start menu or by double-clicking the SPIController software desktop icon. If prompted for a configuration file, select the appropriate one. If not, check the title bar of the window to determine which configuration is loaded. If necessary, choose Cfg Open from the File menu and select the appropriate file based on your part type. Note that the CHIP ID(1) box should be filled to indicate whether the correct SPI controller configuration file is loaded (see Figure 6).

    Figure 6. SPI Controller, CHIP ID(1) Box

  2. Click the New DUT button in the SPIController window (see Figure 7).

    Figure 7. SPI Controller, New DUT Button

  3. In the ADCBase 0 tab of the SPIController window, find the CLOCK DIVIDE(B) box (see Figure 8). If using the clock divider, use the drop-down box to select the correct clock divide ratio, if necessary. See the appropriate part data sheet, the AN-878 Application Note, High Speed ADC SPI Control Software, and the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, for additional information on the available settings.

    Figure 8. SPI Controller, ADCBase0 Page

  4. Note that other settings can be changed on the ADCBase 0 page (see Figure 8) and the ADC A and ADC B pages (see Figure 9) to set up the part in the desired mode. The ADCBase 0 page settings affect the entire part, whereas the settings on the ADC A and ADC B pages affect the selected channel only. See the appropriate part data sheet; the AN-878 Application Note, High Speed ADC SPI Control Software, and the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, for additional information on the available settings.

    Figure 9. SPI Controller, Example ADC A Page

  5. Click the Run button in the VisualAnalog toolbar (see Figure 10).

    Figure 10. Run Button (Encircled in Red) in VisualAnalog Toolbar, Collapsed Display

Adjusting the Amplitude of the Input Signal

The next step is to adjust the amplitude of the input signal for each channel as follows:

  1. Adjust the amplitude of the input signal so that the fundamental is at -1.0 dBFS. Examine the Fund Power reading in the left panel of the VisualAnalog Graph - AD9652 Average FFT window (see Figure 11) to verify this.

    Figure 11. Graph Window of VisualAnalog

  2. Repeat this procedure for Channel B.
  3. Click the disk icon within the Graph window to save the performance plot data as .csv formatted file. See Figure 12 for AD9652 example. Please refer to the respective data sheet of the product of interest for its typical FFT performance.

    Figure 12. Typical FFT, AD9652

Troubleshooting Tips

If the FFT plot appears abnormal, do the following:

  1. If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure you are not overdriving the ADC. Reduce the input level, if necessary.
  2. In VisualAnalog, click the Settings button in the Input Formatter block. Check that Number Format is set to correct encoding (offset binary by default). Repeat for the other channel.

If the FFT appears normal but the performance is poor, check the following:

  1. Make sure that an appropriate filter is used on the analog input.
  2. Make sure that the signal generators for the clock and the analog input are clean (low phase noise).
  3. Change the analog input frequency slightly if noncoherent sampling is being used.
  4. Make sure that the SPI configuration file matches the product being evaluated.

If the FFT window remains blank after Run is clicked, do the following:

  1. Make sure that the evaluation board is securely connected to the HSC-ADC-EVALCZ board.
  2. Make sure that the FPGA has been programmed by verifying that the DONE LED is illuminated on the HSC-ADC-EVALCZ board. If this LED is not illuminated, make sure that the U4 switch on the board is in the correct position for USB CONFIG.
  3. Make sure that the correct FPGA program was installed by clicking the Settings icon in the ADC Data Capture block in VisualAnalog. Then select the FPGA tab and verify that the proper FPGA bin file is selected for the part.

If VisualAnalog indicates that the FIFO Capture timed out, do the following:

  1. Make sure that all power and USB connections are secure.
  2. Probe the DCOA signal at RN801 (Pin 2) on the evaluation board and confirm that a clock signal is present at the ADC sampling rate.
resources/eval/ad9652-310ebz.txt · Last modified: 25 Apr 2022 03:59 by John Xavier Toledo