| Both sides previous revisionPrevious revisionNext revision | Previous revision |
| resources:eval:ad9249-65ebz [13 Nov 2013 02:51] – modify digital reset instruction Doug Ito | resources:eval:ad9249-65ebz [09 Jan 2021 00:22] (current) – user interwiki links Robin Getz |
|---|
| ===== Preface ===== | ===== Preface ===== |
| This user guide describes the [[adi>AD9249|AD9249]] evaluation board [[adi>AD9249|AD9249-65EBZ]], which provides the support circuitry required to operate the ADC in its various modes and configurations. The application software used to interface with the device is also described. | This user guide describes the [[adi>AD9249|AD9249]] evaluation board [[adi>AD9249|AD9249-65EBZ]], which provides the support circuitry required to operate the ADC in its various modes and configurations. The application software used to interface with the device is also described. |
| | \\ |
| | \\ |
| | There are two versions of the [[adi>AD9249|AD9249]] evaluation board [[adi>AD9249|AD9249-65EBZ]]. The earlier version uses two 60 pin Tyco connectors (TE Connectivity AMP Connector 6469169-1) and interfaces to the [[adi>hsadcevalboard|HSC-ADC-EVALDZ]] capture board. The new version has an FMC connector (Samtec ASP-134488-01) and interfaces to the [[adi>hsadcevalboard|HSC-ADC-EVALEZ]] capture board. Both versions of the board perform the same function and this user guide applies to both. All boards ordered from March 2017 and later will be the new version. |
| \\ | \\ |
| \\ | \\ |
| {{ :resources:eval:AD9249-65EBZ_top_level.png?nolink&600 |}} | {{ :resources:eval:AD9249-65EBZ_top_level.png?nolink&600 |}} |
| <WRAP centeralign> | <WRAP centeralign> |
| //Figure 1. Evaluation Board Connection—[[adi>AD9249|AD9249-65EBZ]] (on Left) and [[adi>hsadcevalboard|HSC-ADC-EVALDZ]] (on Right)// | //Figure 1. Evaluation Board Connection—[[adi>AD9249|AD9249-65EBZ]] (Tyco connector version shown on Left) and [[adi>hsadcevalboard|HSC-ADC-EVALDZ]] (on Right)// |
| | </WRAP> |
| | {{ :resources:eval:wiki_diagram_ad9249-65ebz_with_hsc-adc-evalez.png |}} |
| | <WRAP centeralign> |
| | //Figure 1A. Evaluation Board Connection—[[adi>AD9249|AD9249-65EBZ]] (FMC connector version shown on Left) and [[adi>hsadcevalboard|HSC-ADC-EVALEZ]] (on Right)// |
| </WRAP> | </WRAP> |
| |
| ===== Helpful Documents ===== | ===== Helpful Documents ===== |
| * [[adi>AD9249|AD9249]] data sheet | * [[adi>AD9249|AD9249]] data sheet |
| * High speed ADC FIFO evaluation kit ([[adi>hsadcevalboard|HSC-ADC-EVALDZ]]) | * High speed ADC FIFO evaluation kit ([[adi>hsadcevalboard|HSC-ADC-EVALDZ]] or [[adi>hsadcevalboard|HSC-ADC-EVALEZ]]) |
| * HSC-ADC-EVALDZ Wiki Guide [[http://wiki.analog.com/resources/eval/hsc-adc-evald]] | * Capture Board Wiki Guide [[/resources/eval/hsc-adc-evald]] or [[/resources/eval/hsc-adc-evale]] |
| * [[adi>an-905|AN-905 Application Note]], //VisualAnalog Converter Evaluation Tool Version 1.0 User Manual// | * [[adi>an-905|AN-905 Application Note]], //VisualAnalog Converter Evaluation Tool Version 1.0 User Manual// |
| * [[adi>an-878|AN-878 Application Note]], //High Speed ADC SPI Control Software// | * [[adi>an-878|AN-878 Application Note]], //High Speed ADC SPI Control Software// |
| |
| ===== Design and Integration Files ===== | ===== Design and Integration Files ===== |
| * [[adi>static/imported-files/eval_boards/AD9249_Design_Integration.zip|Schematics, layout files, bill of materials]] <Coming Soon> | * [[adi>static/imported-files/eval_boards/AD9249_Design_Integration.zip|Tyco Connector Version Schematics, layout files, bill of materials]] |
| | * {{:resources:eval:ad9249_fmc_brd_designfiles.zip|FMC Connector Version Schematics, layout files, bill of materials}} |
| ===== Equipment Needed ===== | ===== Equipment Needed ===== |
| * Analog signal source(s) and antialiasing filter(s) | * Analog signal source(s) and antialiasing filter(s) |
| * Sample clock source (if not using the on-board crystal oscillator) | * Sample clock source (if not using the on-board crystal oscillator) |
| * Switching power supply (6.0V, 2.5A) for AD9249-65EBZ | * Switching power supply (6.0V, 2.5A) for AD9249-65EBZ |
| * Switching power supply (12V, 3,3A) for HSC-ADC-EVALDZ | * Switching power supply (12V, 3,3A) for HSC-ADC-EVALDZ or HSC-ADC-EVALEZ |
| * PC running Windows® | * PC running Windows® |
| * USB 2.0 port | * USB 2.0 port |
| * [[adi>AD9249|AD9249-65EBZ]] board | * [[adi>AD9249|AD9249-65EBZ]] board |
| * [[adi>hsadcevalboard|HSC-ADC-EVALDZ]] FPGA-based data capture kit | * [[adi>hsadcevalboard|HSC-ADC-EVALDZ]] (capture board for Tyco Connector Version) or [[adi>hsadcevalboard|HSC-ADC-EVALEZ]] (capture board for FMC Connector Version) FPGA-based data capture kit |
| |
| ===== Getting Started ===== | ===== Getting Started ===== |
| ==== Configuring the Board ==== | ==== Configuring the Board ==== |
| Before using the software for testing, configure the evaluation board as follows: | Before using the software for testing, configure the evaluation board as follows: |
| - Connect the evaluation board to the data capture board, as shown in Figure 1. | - Connect the evaluation board to the data capture board, as shown in Figure 1. The Tyco connector version slides horizontally to connect to the [[adi>hsadcevalboard|HSC-ADC-EVALDZ]]. For the FMC connector version, align the FMC connector of the [[adi>AD9249|AD9249-65EBZ]] over the connector on the [[adi>hsadcevalboard|HSC-ADC-EVALEZ]], and carefully press them together. Note that FMC connectors often come from the factory with a sticker that prevents connection. Remove this sticker (if present) before attempting to make the connection. |
| - On the ADC evaluation board, confirm that the jumpers are installed as shown in Figure 2. | - On the ADC evaluation board, confirm that the jumpers are installed as shown in Figure 2. |
| - Connect one 6V, 2.5A switching power supply (such as the CUI, Inc., EPS060250UH-PHP-SZ that is supplied) to the [[adi>AD9249|AD9249-65EBZ]]. | - Connect one 6V, 2.5A switching power supply (such as the CUI, Inc., EPS060250UH-PHP-SZ that is supplied) to the [[adi>AD9249|AD9249-65EBZ]]. |
| - Connect the 12V, 3.3A switching power supply to the [[adi>hsadcevalboard|HSC-ADC-EVALDZ]] board. | - Connect the 12V, 3.3A switching power supply to the [[adi>hsadcevalboard|HSC-ADC-EVALDZ]] or [[adi>hsadcevalboard|HSC-ADC-EVALEZ]] board. |
| - Connect the [[adi>hsadcevalboard|HSC-ADC-EVALDZ]] board (P702) to the PC using a USB cable. | - Connect the capture board to the PC using a USB cable. |
| - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal to the desired channel(s). Use a shielded, RG-58, 50Ω coaxial cable (optimally 1 m or shorter) to connect the signal generator. For best results, use a narrow-band, band-pass filter with 50Ω terminations and an appropriate center frequency. (Analog Devices, Inc. uses TTE, Allen Avionics, and K&L band-pass filters.) | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal to the desired channel(s). Use a shielded, RG-58, 50Ω coaxial cable (optimally 1 m or shorter) to connect the signal generator. For best results, use a narrow-band, band-pass filter with 50Ω terminations and an appropriate center frequency. (Analog Devices, Inc. uses TTE, Allen Avionics, and K&L band-pass filters.) |
| |
| The evaluation board provides the support circuitry required to operate the [[adi>AD9249|AD9249]] in its various modes and configurations. Figure 1 shows the typical bench characterization setup used to evaluate AC performance. It is critical that the signal sources used for the analog input and clock have very low phase noise (ideally ~100 fs rms jitter) to realize the optimum performance of the signal chain. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is necessary to achieve the specified noise performance.\\ | The evaluation board provides the support circuitry required to operate the [[adi>AD9249|AD9249]] in its various modes and configurations. Figure 1 shows the typical bench characterization setup used to evaluate AC performance. It is critical that the signal sources used for the analog input and clock have very low phase noise (ideally ~100 fs rms jitter) to realize the optimum performance of the signal chain. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is necessary to achieve the specified noise performance.\\ |
| \\ | \\ |
| See [[adi>9249ce01a_designsupport|AD9249 Design Support <Coming Soon>]] for the complete schematics and layout diagrams. These diagrams demonstrate the routing and grounding techniques that should be applied at the system level when designing application boards using these converters.\\ | See [[adi>static/imported-files/eval_boards/AD9249_Design_Integration.zip|AD9249 Design Support]] for the schematics and layout diagrams of the Tyco connector version. The files for the FMC connector version will be added to this Wiki after the board is in production. These diagrams demonstrate the routing and grounding techniques that should be applied at the system level when designing application boards using these converters.\\ |
| |
| ==== Power Supplies ==== | ==== Power Supplies ==== |
| This evaluation board comes with a wall-mountable switching power supply that provides a 6V, 2A maximum output. Connect the supply to a 100V ac to 240V ac, 47Hz to 63Hz wall outlet. The output from the supply is provided through a 2.1mm inner diameter jack that connects to the printed circuit board (PCB) at P101. The 6V supply is fused and conditioned on the PCB before connecting to the low dropout linear regulators that supply the proper bias to each of the various sections on the board.\\ | This evaluation board comes with a wall-mountable switching power supply that provides a 6V, 2A maximum output. Connect the supply to a 100V ac to 240V ac, 47Hz to 63Hz wall outlet. The output from the supply is provided through a 2.1mm inner diameter jack that connects to the printed circuit board (PCB) at P101. The 6V supply is fused and conditioned on the PCB before connecting to the low dropout linear regulators that supply the proper bias to each of the various sections on the board.\\ |
| \\ | \\ |
| The evaluation board can be powered in a nondefault condition using external bench power supplies. To do this, remove the E102, E103, E110, and E113 ferrite beads to disconnect the on-board LDOs from the power planes. Note that in some board configurations some of these might already be uninstalled. P102 and P103 headers can be installed to facilitate connection of external bench supplies to the board. E106, E107, E108 and E109 need to be populated to connect P102 and P103 to the board power domains. A 1.8V , 0.5A supply is needed for both 1.8V_DUT_AVDD and 1.8V_DRVDD. Although the voltage requirements are the same for 1.8V_DUT_AVDD and 1.8V_DRVDD, it is recommended that separate supplies be used for each of these.\\ | The evaluation board can be powered in a nondefault condition using external bench power supplies. To do this, remove the E102, E103, E110, and E113 ferrite beads to disconnect the on-board regulators from the power planes. Note that in some board configurations some of these might already be uninstalled. P102 and P103 headers can be installed to facilitate connection of external bench supplies to the board. E106, E107, E108 and E109 need to be populated to connect P102 and P103 to the board power domains. A 1.8V , 0.5A supply is needed for both 1.8V_DUT_AVDD and 1.8V_DRVDD. Although the voltage requirements are the same for 1.8V_DUT_AVDD and 1.8V_DRVDD, it is recommended that separate supplies be used for each of these.\\ |
| \\ | \\ |
| Two additional supplies, 3.3V_CLK and 1.8V_DVDD, are used to power additional on board circuitry. If used, these supplies should each have at least 0.5A current capability.\\ | Two additional supplies, 3.3V_CLK and 1.8V_DVDD, are used to power additional on board circuitry. If used, these supplies should each have at least 0.5A current capability.\\ |
| |
| ==== Output Signals ==== | ==== Output Signals ==== |
| The default setup uses the Analog Devices high speed converter evaluation platform ([[adi>hsadcevalboard|HSC-ADC-EVALDZ]]) for data capture. The serial LVDS outputs from the ADC are routed to J1 and J2 using 100Ω differential traces. For more information on the data capture board and its optional settings, visit [[adi>hsadcevalboard|www.analog.com/hsadcevalboard]]. | The default setup uses the Analog Devices high speed converter evaluation platform ([[adi>hsadcevalboard|HSC-ADC-EVALDZ]] or [[adi>hsadcevalboard|HSC-ADC-EVALEZ]]) for data capture. The serial LVDS outputs from the ADC are routed to J1 and J2 (on the Tyco Connector version) or P2 (on the FMC Connector version). For more information on the data capture boards, visit [[adi>hsadcevalboard|www.analog.com/hsadcevalboard]]. |
| |
| ===== Jumper Settings ===== | ===== Jumper Settings ===== |
| Set the jumper settings/link options on the evaluation board for the required operating modes before powering on the board. The functions of the jumpers are described in Table 1. Figure 2 shows the default jumper settings. | Set the jumper settings/link options on the evaluation board for the required operating modes before powering on the board. The functions of the jumpers are described in Table 1. Figure 2 shows the default jumper settings. The same jumper settings are applicable to both the Tyco Connector version and the FMC Connector Version. |
| \\ | \\ |
| == Table 1. Jumper Settings == | == Table 1. Jumper Settings == |
| ^Jumper ^Description | | ^Jumper ^Description | |
| |J204 |Use this jumper to power down the ADC. Using the SPI, the PDWN pin can be configured to invoke the STBY (standby) function instead of power down.| | |J204 |Use this jumper to power down the ADC. Using the SPI, the PDWN pin can be configured to invoke the STBY (standby) function instead of power down.| |
| |P1 |This jumper sets the ADC for SPI communications with the [[adi>hsadcevalboard|HSC-ADC-EVALDZ]].\\ Connect Pin 1 to Pin 2 for SDIO, Pin 4 to Pin 5 for SCLK, Pin 8 to Pin 9 for CSB1 and Pin 11 to Pin 12 for CSB2.| | |P1 |This jumper sets the ADC for SPI communications with the [[adi>hsadcevalboard|HSC-ADC-EVALDZ]] or [[adi>hsadcevalboard|HSC-ADC-EVALEZ]].\\ Connect Pin 1 to Pin 2 for SDIO, Pin 4 to Pin 5 for SCLK, Pin 8 to Pin 9 for CSB1 and Pin 11 to Pin 12 for CSB2.| |
| |J804 |This jumper enables the on-board crystal oscillator. Remove this jumper (and optimally C810) if an external off-board clock source is used.| | |J804 |This jumper enables the on-board crystal oscillator. Remove this jumper (and optimally C810) if an external off-board clock source is used.| |
| |J202 |This jumper selects between internal V<sub>REF</sub> and external V<sub>REF</sub>.\\ To choose the ADC's internal 1V reference, connect Pin 3 (DUT_SENSE) to Pin 5 (GND) as shown in Figure 2.\\ To use the on-board [[adi>AD822|AD822]] buffered reference, connect Pin 2 (DUT_SENSE) to Pin 1 (AVDD), and connect Pin 4 (DUT_VREF) to Pin 6 (EXT_REF). Adjust external VREF to be 1.0V using potentiometer R202.\\ To apply a reference voltage from an external off-board source, connect Pin 2 (DUT_SENSE) to Pin 1 (AVDD) and apply the reference voltage to Pin 4 (DUT_VREF). The AD9249 reference voltage is specified to be 1.0 V.| | |J202 |This jumper selects between internal V<sub>REF</sub> and external V<sub>REF</sub>.\\ To choose the ADC's internal 1V reference, connect Pin 3 (DUT_SENSE) to Pin 5 (GND) as shown in Figure 2.\\ To use the on-board [[adi>AD822|AD822]] buffered reference (Tyco connector version) or [[adi>ADR130|ADR130]] reference (FMC connector version), connect Pin 2 (DUT_SENSE) to Pin 1 (AVDD), and connect Pin 4 (DUT_VREF) to Pin 6 (EXT_REF). Adjust external VREF to be 1.0V using potentiometer R202 (Tyco connector version only).\\ To apply a reference voltage from an external off-board source, connect Pin 2 (DUT_SENSE) to Pin 1 (AVDD) and apply the reference voltage to Pin 4 (DUT_VREF). The AD9249 reference voltage is specified to be 1.0 V.| |
| \\ | \\ |
| {{ :resources:eval:AD9249_65ebz_default_jumpers.png?nolink&600 |}} | {{ :resources:eval:AD9249_65ebz_default_jumpers.png?nolink&600 |}} |
| <WRAP centeralign> | <WRAP centeralign> |
| //Figure 2. Default Jumper Connections for [[adi>AD9249|AD9249-65EBZ]] Board// | //Figure 2. Default Jumper Connections for [[adi>AD9249|AD9249-65EBZ]] Board (Tyco connector version shown)// |
| | </WRAP> \\ |
| | {{ :resources:eval:ad9249-65ebz_jumper_connections.png?600 |}} |
| | <WRAP centeralign> |
| | //Figure 2A. Default Jumper Connections for [[adi>AD9249|AD9249-65EBZ]] Board (FMC connector version shown)// |
| </WRAP> \\ | </WRAP> \\ |
| |
| ===== Evaluation Board Circuitry ===== | ===== Evaluation Board Circuitry ===== |
| This section explains the default and optional ADC settings or modes allowed on the [[adi>AD9249|AD9249-65EBZ]] board.\\ | This section explains the default and optional ADC settings or modes allowed on the [[adi>AD9249|AD9249-65EBZ]] board.\\ |
| - Start VisualAnalog on the connected PC. The appropriate part type should be listed in the status bar of the **VisualAnalog – New Canvas** window. Select the template that corresponds to the type of testing to be performed (see Figure 3).{{ :resources:eval:AD9249_VA_New_Canvas_window.PNG?nolink&500 |}}<WRAP centeralign>//Figure 3. VisualAnalog, New Canvas Window//</WRAP>\\ | - Start VisualAnalog on the connected PC. The appropriate part type should be listed in the status bar of the **VisualAnalog – New Canvas** window. Select the template that corresponds to the type of testing to be performed (see Figure 3).{{ :resources:eval:AD9249_VA_New_Canvas_window.PNG?nolink&500 |}}<WRAP centeralign>//Figure 3. VisualAnalog, New Canvas Window//</WRAP>\\ |
| - After the template is selected, a message might appear asking if the default configuration can be used to program the FPGA (see Figure 4). If this message appears, click **Yes**, and the window will close.\\ {{ :resources:eval:10235-005.png?400 |}}<WRAP centeralign>//Figure 4. VisualAnalog Default Configuration Message//</WRAP>\\ | - After the template is selected, a message might appear asking if the default configuration can be used to program the FPGA (see Figure 4). If this message appears, click **Yes**, and the window will close.\\ {{ :resources:eval:10235-005.png?400 |}}<WRAP centeralign>//Figure 4. VisualAnalog Default Configuration Message//</WRAP>\\ |
| - To change features to settings other than the default settings, click the **Expand Display** button, located on the bottom right corner of the window (see Figure 5), to see what is shown in Figure 6.\\ | - To view the canvas and associated functional blocks, click the **Expand Display** button, located on the bottom right corner of the window (see Figure 5), to see what is shown in Figure 6.\\ |
| - Change the features and capture settings by consulting the detailed instructions in the [[adi>AN-905|AN-905 Application Note]], //VisualAnalog Converter Evaluation Tool Version 1.0 User Manual//.{{ :resources:eval:AD9249_VA_toolbar_collapsed.PNG?nolink&500 |}} | {{ :resources:eval:AD9249_VA_toolbar_collapsed.PNG?nolink&500 |}} |
| <WRAP centeralign>//Figure 5. VisualAnalog Window Toolbar, Collapsed Display// | <WRAP centeralign>//Figure 5. VisualAnalog Window Toolbar, Collapsed Display// |
| \\ | \\ |
| </WRAP>{{ :resources:eval:AD9249_VA_avg_FFT_window_2ch_expanded.PNG?nolink&700 |}} | </WRAP>{{ :resources:eval:AD9249_VA_avg_FFT_window_2ch_expanded.PNG?nolink&700 |}} |
| <WRAP centeralign>//Figure 6. VisualAnalog, Main Window Expanded Display//</WRAP> | <WRAP centeralign>//Figure 6. VisualAnalog, Main Window Expanded Display//</WRAP> |
| | 4. To configure VisualAnalog to operate with the AD9249, push the Settings button on the ADCDataCapture block, as shown in Figure 7. |
| | {{ :resources:eval:AD9656_ADC_DataCaptureSettings_button.PNG?nolink&200 |}} |
| | <WRAP centeralign>//Figure 7. VisualAnalog ADC Data Capture Block//</WRAP> |
| | \\ |
| | \\ |
| | 5. In the ADC Data Capture Settings Window, General Tab, select AD9249 to be the device, enter the sample clock frequency (65 is the default value), as shown in Figure 8. The sample frequency entered here is used for scaling of frequency values in test results and graphs. In the Output Data field, the channels to be tested are selected, as well as the FFT capture depth ("Length"). Note that the total of the capture depths for all selected channels cannot exceed 256k. |
| | {{ :resources:eval:AD9249_ADC_DataCaptureSettings_GeneralTab.PNG?nolink&500 |}} |
| | <WRAP centeralign>//Figure 8. VisualAnalog ADC Data Capture Settings Window, General Tab//</WRAP> |
| | \\ |
| | \\ |
| | 6. In the ADC Data Capture Settings Window, Capture Board Tab, enter 30 in the Fill Delay field. Push the Browse button to navigate to the FPGA program file for the AD9249. The default installation location and filename will be similar to:\\ |
| | C:\Program Files\Analog Devices\VisualAnalog\Hardware\HADv6\AD9249_hadv6.mcs (for the Tyco Connector Version)\\ |
| | C:\Program Files\Analog Devices\VisualAnalog\Hardware\HADv6\ad9249_evalez_20151007_1817.mcs (for the FMC Connector Version)\\ |
| | Push the **program button**. |
| | {{ :resources:eval:AD9249_ADC_DataCaptureSettings_CaptureBoardTab.PNG?nolink&500 |}} |
| | <WRAP centeralign>//Figure 9. VisualAnalog ADC Data Capture Settings Window, Capture Board Tab//</WRAP> |
| | \\ |
| | \\ |
| | 7. VisualAnalog is now setup to work with the AD9249-65EBZ in the default condition. Other VisualAnalog features and capture settings are documented in the [[adi>AN-905|AN-905 Application Note]], //VisualAnalog Converter Evaluation Tool Version 1.0 User Manual//. |
| ===== Evaluation And Test ===== | ===== Evaluation And Test ===== |
| ==== Setting up the SPI Controller Software ==== | ==== Setting up the SPI Controller Software ==== |
| After the ADC data capture board setup is complete, set up the SPI controller software using the following procedure:\\ | After the ADC data capture board setup is complete, set up the SPI controller software using the following procedure:\\ |
| - Open the SPI controller software by going to the **Start** menu or by double-clicking the **SPIController** software desktop icon. If prompted for a configuration file, select .cfg file whose name begins with AD9249. If not prompted, check the title bar of the window to determine which configuration is loaded. If necessary, choose **Cfg Open** from the **File** menu and select the appropriate file based on your part type. Note that the **CHIP ID(1)** box should be filled to indicate whether the correct SPI controller configuration file is loaded (see Figure 7).{{ :resources:eval:AD9249_SPIController_Global_tab_ChipID.PNG?nolink&600 |}}<WRAP centeralign>//Figure 7. SPI Controller, CHIP ID(1) Box//</WRAP>\\ | - Open the SPI controller software by going to the **Start** menu or by double-clicking the **SPIController** software desktop icon. If prompted for a configuration file, select .cfg file whose name begins with AD9249. If not prompted, check the title bar of the window to determine which configuration is loaded. If necessary, choose **Cfg Open** from the **File** menu and select the appropriate file based on your part type. Note that the **CHIP ID(1)** box should be filled to indicate whether the correct SPI controller configuration file is loaded (see Figure 10).{{ :resources:eval:AD9249_SPIController_Global_tab_ChipID.PNG?nolink&600 |}}<WRAP centeralign>//Figure 10. SPI Controller, CHIP ID(1) Box//</WRAP>\\ |
| - Click the **New DUT** button in the **SPIController** window (see Figure 8){{ :resources:eval:AD9249_spicontroller_global_tab_newdUT_button.png?nolink&600 |}}<WRAP centeralign>//Figure 8. SPI Controller, New DUT Button//</WRAP>\\ | - Click the **New DUT** button in the **SPIController** window (see Figure 11){{ :resources:eval:AD9249_spicontroller_global_tab_newdUT_button.png?nolink&600 |}}<WRAP centeralign>//Figure 11. SPI Controller, New DUT Button//</WRAP>\\ |
| - In the **ADCBase 0** tab of the **SPIController** window, find the **CLOCK DIVIDE(B)** box (see Figure 9), and the **MODES(8)** box (see Figure 10). If using the clock divider, use the drop-down box to select the correct clock divide ratio, if necessary. If there is any interruption of the ADC clock during power-up or during operation, a Digital Reset may be needed to re-initialize the ADC (Figure 10). For additional information, refer to the data sheet, the [[adi>an-878|AN-878 Application Note]], //High Speed ADC SPI Control Software//, and the [[adi>an-877|AN-877 Application Note]], //Interfacing to High Speed ADCs via SPI//.{{ :resources:eval:AD9249_SPIController_ADCBase0_tab_ClkDiv.png?nolink&600 |}}<WRAP centeralign>//Figure 9. SPI Controller, CLOCK DIVIDE(B) Box//</WRAP>\\ {{ :resources:eval:AD9249_SPIController_ADCBase0_tab_DigReset.png?nolink&600 |}}<WRAP centeralign>//Figure 10. SPI Controller, Chip Power Mode - Digital Reset Selection//</WRAP>\\ | - In the **ADCBase 0** tab of the **SPIController** window, find the **CLOCK DIVIDE(B)** box (see Figure 12), and the **MODES(8)** box (see Figure 13). If using the clock divider, use the drop-down box to select the correct clock divide ratio, if necessary. If there is any interruption of the ADC clock during power-up or during operation, a Digital Reset may be needed to re-initialize the ADC (Figure 13). For additional information, refer to the data sheet, the [[adi>an-878|AN-878 Application Note]], //High Speed ADC SPI Control Software//, and the [[adi>an-877|AN-877 Application Note]], //Interfacing to High Speed ADCs via SPI//.{{ :resources:eval:AD9249_SPIController_ADCBase0_tab_ClkDiv.png?nolink&600 |}}<WRAP centeralign>//Figure 12. SPI Controller, CLOCK DIVIDE(B) Box//</WRAP>\\ {{ :resources:eval:AD9249_SPIController_ADCBase0_tab_DigReset.png?nolink&600 |}}<WRAP centeralign>//Figure 13. SPI Controller, Chip Power Mode - Digital Reset Selection//</WRAP>\\ |
| - Note that other settings can be changed on the **ADCBase 0 tab** (see Figure 9) and the **ADC A** through **ADC H** tabs (see Figure 11) to set up the part in the desired mode. The **ADCBase 0** tab settings affect the entire part, whereas the settings on the **ADC A** through **ADC H** tabs each affect the selected channel only. The B1 (Bank1), B2 (Bank2) and All buttons at the right end of the SPIController button row (as seen in Figure 10 and Figure 11) determine which bank of ADCs is affected by the SPIController settings. The All button is pushed by default which means that the **ADCBase 0** tab settings affect all channels on both ADC banks. The settings in the **ADC A** through **ADC H** will likewise affect their respective channels in both banks. For example, with the All button pushed, settings in the **ADC A** tab will affect channels A1 and A2. If the All button is un-pushed and the B1 (Bank1) button remains pushed, the settings in the **ADC A** tab will only affect channel A1. See the data sheet, the [[adi>an-878|AN-878 Application Note]], //High Speed ADC SPI Control Software//, and the [[adi>an-877|AN-877 Application Note]], //Interfacing to High Speed ADCs via SPI//, for additional information on the available settings.{{ :resources:eval:AD9249_SPIController_ADCA_tab.PNG?nolink&600 |}}<WRAP centeralign>//Figure 11. SPI Controller, Example ADC A Page//</WRAP>\\ | - Note that other settings can be changed on the **ADCBase 0 tab** (see Figure 12) and the **ADC A** through **ADC H** tabs (see Figure 14) to set up the part in the desired mode. The **ADCBase 0** tab settings affect the entire part, whereas the settings on the **ADC A** through **ADC H** tabs each affect the selected channel only. The B1 (Bank1), B2 (Bank2) and All buttons at the right end of the SPIController button row (as seen in Figure 13 and Figure 14) determine which bank of ADCs is affected by the SPIController settings. The All button is pushed by default which means that the **ADCBase 0** tab settings affect all channels on both ADC banks. The settings in the **ADC A** through **ADC H** will likewise affect their respective channels in both banks. For example, with the All button pushed, settings in the **ADC A** tab will affect channels A1 and A2. If the All button is un-pushed and the B1 (Bank1) button remains pushed, the settings in the **ADC A** tab will only affect channel A1. See the data sheet, the [[adi>an-878|AN-878 Application Note]], //High Speed ADC SPI Control Software//, and the [[adi>an-877|AN-877 Application Note]], //Interfacing to High Speed ADCs via SPI//, for additional information on the available settings.{{ :resources:eval:AD9249_SPIController_ADCA_tab.PNG?nolink&600 |}}<WRAP centeralign>//Figure 14. SPI Controller, Example ADC A Page//</WRAP>\\ |
| - Invoke a Digital Reset as shown in Figure 10 before testing. After selecting Reset, select Chip run to return to normal operation. | - Invoke a Digital Reset as shown in Figure 13 before testing. After selecting Reset, select Chip run to return to normal operation. |
| - To begin testing, click the **Run** or **Continuous Run** button in the **VisualAnalog** toolbar (see Figure 12).{{ :resources:eval:AD9249_VA_toolbar_collapsed_run_button.PNG?nolink&600 |}}<WRAP centeralign>//Figure 12. Run/Continuous Run Buttons (Encircled in Red) in VisualAnalog Toolbar, Collapsed Display//</WRAP>\\ | - To begin testing, click the **Run** or **Continuous Run** button in the **VisualAnalog** toolbar (see Figure 15).{{ :resources:eval:AD9249_VA_toolbar_collapsed_run_button.PNG?nolink&600 |}}<WRAP centeralign>//Figure 15. Run/Continuous Run Buttons (Encircled in Red) in VisualAnalog Toolbar, Collapsed Display//</WRAP>\\ |
| |
| ==== Adjusting the Amplitude of the Input Signal ==== | ==== Adjusting the Amplitude of the Input Signal ==== |
| The next step is to adjust the amplitude of the input signal for each channel as follows: | The next step is to adjust the amplitude of the input signal for each channel as follows: |
| - Adjust the amplitude of the input signal so that the fundamental is at the desired level. Examine the **Fund Power** reading in the left panel of the **VisualAnalog Graph - AD9249 FFT** window (see Figure 13).{{ :resources:eval:AD9249_FFT_example.png?nolink&600 |}}<WRAP centeralign>//Figure 13. Graph Window of VisualAnalog //</WRAP>\\ | - Adjust the amplitude of the input signal so that the fundamental is at the desired level. Examine the **Fund Power** reading in the left panel of the **VisualAnalog Graph - AD9249 FFT** window (see Figure 16).{{ :resources:eval:AD9249_FFT_example.png?nolink&600 |}}<WRAP centeralign>//Figure 16. Graph Window of VisualAnalog //</WRAP>\\ |
| - Repeat this procedure for the other channels, if desired | - Repeat this procedure for the other channels, if desired |
| - Click the floppy-disk icon within the **VisualAnalog Graph - AD9249 FFT** window to save the performance data as a .csv formatted file for plotting or analysis. | - Click the floppy-disk icon within the **VisualAnalog Graph - AD9249 FFT** window to save the performance data as a .csv formatted file for plotting or analysis. |
| Lack of SPI communication will cause difficulty in configuring the ADC. | Lack of SPI communication will cause difficulty in configuring the ADC. |
| * Go to the **Global** tab of the **SPIController** window and push the **Read** button in the **GENERIC READ/WRITE** window. This will read the contents of ADC register 0x00. If SPI communication is working properly and the ADC is powered up, the value 0x18 hexadecimal will appear. If the contents show 0x00, the ADC is not powered up or SPI communication is not working. | * Go to the **Global** tab of the **SPIController** window and push the **Read** button in the **GENERIC READ/WRITE** window. This will read the contents of ADC register 0x00. If SPI communication is working properly and the ADC is powered up, the value 0x18 hexadecimal will appear. If the contents show 0x00, the ADC is not powered up or SPI communication is not working. |
| * Check that there is correct power to the [[adi>AD9249|AD9249-65EBZ]] board, and to the [[adi>hsadcevalboard|HSC-ADC-EVALDZ]]. | * Check that there is correct power to the [[adi>AD9249|AD9249-65EBZ]] board, and to the [[adi>hsadcevalboard|HSC-ADC-EVALDZ]] or [[adi>hsadcevalboard|HSC-ADC-EVALEZ]]. |
| * Check that the USB cable is properly connected from the PC to the [[adi>hsadcevalboard|HSC-ADC-EVALDZ]]. | * Check that the USB cable is properly connected from the PC to the [[adi>hsadcevalboard|HSC-ADC-EVALDZ]] or [[adi>hsadcevalboard|HSC-ADC-EVALEZ]]. |
| * The LED on the **VisualAnalog ADCDataCapture** block should be green. If it is red, push the USB button on the same block to refresh the connection.\\ | * The LED on the **VisualAnalog ADCDataCapture** block should be green. If it is red, push the USB button on the same block to refresh the connection.\\ |
| |
| If the FFT plot appears abnormal, do the following: | If the FFT plot appears abnormal, do the following: |
| * If you see an abnormal noise floor, go to the **ADCBase0** tab of the **SPIController** window and toggle the **Chip Power Mode** in **MODES(8)** from **Chip Run** to **Reset** and back (Figure 10). | * If you see an abnormal noise floor, go to the **ADCBase0** tab of the **SPIController** window and toggle the **Chip Power Mode** in **MODES(8)** from **Chip Run** to **Reset** and back (Figure 13). |
| * If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure that you are not overdriving the ADC. Reduce the input level, if necessary. | * If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure that you are not overdriving the ADC. Reduce the input level, if necessary. |
| * In **VisualAnalog**, click the **Settings** icon in the **Input Formatter** block. Check that **Number Format** is set to the correct encoding (twos complement by default). Check that the **Number Format** in the **VisualAnalog Input Formatter** matches the data format selected in the **SPIController ADCBase0 OUTPUT MODE(14)** window. Repeat for the other channels.\\ | * In **VisualAnalog**, click the **Settings** icon in the **Input Formatter** block. Check that **Number Format** is set to the correct encoding (twos complement by default). Check that the **Number Format** in the **VisualAnalog Input Formatter** matches the data format selected in the **SPIController ADCBase0 OUTPUT MODE(14)** window. Repeat for the other channels.\\ |
| * Make sure that the SPI configuration file matches the product being evaluated.\\ | * Make sure that the SPI configuration file matches the product being evaluated.\\ |
| |
| If the FFT window remains blank after **Run** in VisualAnalog (see Figure 12) is clicked, do the following: | If the FFT window remains blank after **Run** in VisualAnalog (see Figure 15) is clicked, do the following: |
| * Make sure that the evaluation board is securely connected to the [[adi>hsadcevalboard|HSC-ADC-EVALDZ]] board. | * Make sure that the evaluation board is securely connected to the [[adi>hsadcevalboard|HSC-ADC-EVALDZ]] or [[adi>hsadcevalboard|HSC-ADC-EVALEZ]]. |
| * Make sure that the correct FPGA program was installed by clicking the **Settings** icon in the **ADC Data Capture** block in VisualAnalog. Then select the **FPGA** tab and verify that the proper FPGA .mcs file (one containing "AD9249" in the filename) is selected for the part. | * Make sure that the correct FPGA program was installed by clicking the **Settings** icon in the **ADC Data Capture** block in VisualAnalog. Then select the **FPGA** tab and verify that the proper FPGA .mcs file (one containing "AD9249" in the filename) is selected for the part. |
| * Make sure that the FPGA has been programmed by verifying that the **DONE** LED is illuminated on the [[adi>hsadcevalboard|HSC-ADC-EVALDZ]] board. If the **DONE** LED is not illuminated, click the **Settings** icon in the **ADC Data Capture** block in VisualAnalog. Then select the **FPGA** tab and verify that the proper FPGA .mcs file (one containing "AD9249" in the filename) is selected for the part. Then push the **Program** button. The LED should light up.\\ | * Make sure that the FPGA has been programmed by verifying that the **DONE** LED is illuminated on the [[adi>hsadcevalboard|HSC-ADC-EVALDZ]] or [[adi>hsadcevalboard|HSC-ADC-EVALEZ]]. If the **DONE** LED is not illuminated, click the **Settings** icon in the **ADC Data Capture** block in VisualAnalog. Then select the **FPGA** tab and verify that the proper FPGA .mcs file (one containing "AD9249" in the filename) is selected for the part. Then push the **Program** button. The LED should light up.\\ |
