This user guide describes the AD9249 evaluation board AD9249-65EBZ, which provides the support circuitry required to operate the ADC in its various modes and configurations. The application software used to interface with the device is also described.
The AD9249 data sheet provides additional information and should be consulted when using the evaluation board. All documents and software tools are available at www.analog.com/hsadcevalboard. For additional information or questions, send an email to email@example.com.
This section provides quick start procedures for using the AD9249-65EBZ board. Both the default and optional ADC settings are described.
Before using the software for testing, configure the evaluation board as follows:
The evaluation board provides the support circuitry required to operate the AD9249 in its various modes and configurations. Figure 1 shows the typical bench characterization setup used to evaluate AC performance. It is critical that the signal sources used for the analog input and clock have very low phase noise (ideally ~100 fs rms jitter) to realize the optimum performance of the signal chain. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is necessary to achieve the specified noise performance.
See AD9249 Design Support for the schematics and layout diagrams. These diagrams demonstrate the routing and grounding techniques that should be applied at the system level when designing application boards using these converters.
This evaluation board comes with a wall-mountable switching power supply that provides a 6V, 2A maximum output. Connect the supply to a 100V ac to 240V ac, 47Hz to 63Hz wall outlet. The output from the supply is provided through a 2.1mm inner diameter jack that connects to the printed circuit board (PCB) at P101. The 6V supply is fused and conditioned on the PCB before connecting to the low dropout linear regulators that supply the proper bias to each of the various sections on the board.
The evaluation board can be powered in a nondefault condition using external bench power supplies. To do this, remove the E102, E103, E110, and E113 ferrite beads to disconnect the on-board LDOs from the power planes. Note that in some board configurations some of these might already be uninstalled. P102 and P103 headers can be installed to facilitate connection of external bench supplies to the board. E106, E107, E108 and E109 need to be populated to connect P102 and P103 to the board power domains. A 1.8V , 0.5A supply is needed for both 1.8V_DUT_AVDD and 1.8V_DRVDD. Although the voltage requirements are the same for 1.8V_DUT_AVDD and 1.8V_DRVDD, it is recommended that separate supplies be used for each of these.
Two additional supplies, 3.3V_CLK and 1.8V_DVDD, are used to power additional on board circuitry. If used, these supplies should each have at least 0.5A current capability.
When connecting the ADC clock and analog source, use clean signal generators with low phase noise, such as the Rohde & Schwarz SMA, or an equivalent. Use a shielded, RG-58, 50Ω coaxial cable (optimally 1 m or shorter) for connecting to the evaluation board. Enter the desired frequency and amplitude (see the Specifications section in the data sheet). When connecting the analog input source, use of a multipole, narrow-band band-pass filter with 50Ω terminations is recommended. Analog Devices uses band-pass filters from TTE and K&L Microwave, Inc. Connect the filters as close to the evaluation board as possible.
If an external clock source is used instead of the onboard crystal oscillator, it should also be supplied with a clean signal generator as previously specified for the analog input signals. Analog Devices evaluation boards typically can accept ~2.8V p-p or 13 dBm sine wave input for the clock at the board SMA clock connector. If an external off-board clock source is used, remove the jumper on J804, and C810, to disable and disconnect the on-board crystal oscillator.
The default setup uses the Analog Devices high speed converter evaluation platform (HSC-ADC-EVALDZ) for data capture. The serial LVDS outputs from the ADC are routed to J1 and J2 using 100Ω differential traces. For more information on the data capture board and its optional settings, visit www.analog.com/hsadcevalboard.
Set the jumper settings/link options on the evaluation board for the required operating modes before powering on the board. The functions of the jumpers are described in Table 1. Figure 2 shows the default jumper settings.
|J204||Use this jumper to power down the ADC. Using the SPI, the PDWN pin can be configured to invoke the STBY (standby) function instead of power down.|
|P1||This jumper sets the ADC for SPI communications with the HSC-ADC-EVALDZ.
Connect Pin 1 to Pin 2 for SDIO, Pin 4 to Pin 5 for SCLK, Pin 8 to Pin 9 for CSB1 and Pin 11 to Pin 12 for CSB2.
|J804||This jumper enables the on-board crystal oscillator. Remove this jumper (and optimally C810) if an external off-board clock source is used.|
|J202||This jumper selects between internal VREF and external VREF.
To choose the ADC's internal 1V reference, connect Pin 3 (DUT_SENSE) to Pin 5 (GND) as shown in Figure 2.
To use the on-board AD822 buffered reference, connect Pin 2 (DUT_SENSE) to Pin 1 (AVDD), and connect Pin 4 (DUT_VREF) to Pin 6 (EXT_REF). Adjust external VREF to be 1.0V using potentiometer R202.
To apply a reference voltage from an external off-board source, connect Pin 2 (DUT_SENSE) to Pin 1 (AVDD) and apply the reference voltage to Pin 4 (DUT_VREF). The AD9249 reference voltage is specified to be 1.0 V.
Figure 2. Default Jumper Connections for AD9249-65EBZ Board
This section explains the default and optional ADC settings or modes allowed on the AD9249-65EBZ board.
Connect the switching power supply that is supplied in the evaluation kit between a rated 100V ac to 240V ac, 47Hz to 63Hz wall outlet and P101.
The sixteen channel inputs on the evaluation board are set up for a double balun-coupled analog input with a 50Ω impedance. The default analog input configuration supports analog input frequencies of up to ~200 MHz.
RBIAS has a default setting of 10 kΩ (R205 and R288) to ground and is used to set the ADC core bias current. Note that using a resistor value other than 10kΩ, 1% resistors for RBIAS1 and RBIAS2 may degrade the performance of the device.
The default clock input circuit is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T801) that adds negligible jitter to the clock path. The clock input is 50 Ω terminated and ac-coupled to handle single-ended sinusoidal inputs. The transformer converts the single-ended input to a differential signal that is clipped by CR801 before entering the ADC clock inputs. The AD9249 ADC is equipped with an internal clock divider (programmable divide ratios of 1 through 8) to facilitate usage with higher frequency clocks. When using the internal divider and a higher input clock frequency, remove CR801 to preserve the slew rate of the clock signal.
The AD9249-65EBZ board is set up to be clocked through the transformer-coupled input network from the crystal oscillator, Y801. If a different clock source is desired, remove C810 (optional) and Jumper J804 to disable the oscillator from running and connect the external clock source to the SMA connector, J802 (labeled CLK+).
The AD9249 ADC can operate in pin mode if there is no need to program and change the default modes of operation via the SPI. For applications that do not require SPI mode operation, the CSB1 and CSB2 pins are tied to 1.8V_DVDD by removing jumpers on Pin 8 and Pin 11 of P1. In this configuration SDIO/DFS (P1 Pin 2) controls the output data format, and SCLK/DTP (P1 Pin 5) controls the digital output test pattern. Table 2 and Table 3 specify the settings for pin mode operation.
|SDIO/DFS (P1 Pin 2) Voltage||Device Mode|
|1.8V_DUT_AVDD (jumper P1 Pin 2 to Pin 3)||Twos Complement|
|GND (“float” P1 Pin 2)||Offset Binary|
|SCLK/DTP (P1 Pin 5) Voltage||Output Format|
|GND (“float” P1 Pin 5)||Normal Operation|
|1.8V_DUT_AVDD (jumper P1 Pin 5 to Pin 6)||10 0000 0000 0000|
Note that the above settings only apply when CSB1 and CSB2 are tied high (P1 Pin 8 and Pin 11 “floating”) at power up.
Additional information on the Standalone (PIN) Mode is provided in the AD9249 data sheet.
To operate the device under test (DUT) using the SPI, follow the jumper settings for P1 as shown in Table 1.
The installers for VisualAnalog and SPIController are in the following locations:
Run these installers on the PC that is connected to the evaluation setup before proceeding.
After configuring the board hardware, set up the ADC data capture using the following steps:
Figure 3. VisualAnalog, New Canvas Window
Figure 5. VisualAnalog Window Toolbar, Collapsed Display
Figure 6. VisualAnalog, Main Window Expanded Display
4. To configure VisualAnalog to operate with the AD9249, push the Settings button on the ADCDataCapture block, as shown in Figure 7.
Figure 7. VisualAnalog ADC Data Capture Block
5. In the ADC Data Capture Settings Window, General Tab, select AD9249 to be the device, enter the sample clock frequency (65 is the default value), as shown in Figure 8. The sample frequency entered here is used for scaling of frequency values in test results and graphs. In the Output Data field, the channels to be tested are selected, as well as the FFT capture depth (“Length”). Note that the total of the capture depths for all selected channels cannot exceed 256k.
Figure 8. VisualAnalog ADC Data Capture Settings Window, General Tab
6. In the ADC Data Capture Settings Window, Capture Board Tab, enter 30 in the Fill Delay field. Push the Browse button to navigate to the FPGA program file for the AD9249. The default installation location and filename will be similar to: C:\Program Files\Analog Devices\VisualAnalog\Hardware\HADv6\AD9249_hadv6.mcs
Push the program button.
Figure 9. VisualAnalog ADC Data Capture Settings Window, Capture Board Tab
7. VisualAnalog is now setup to work with the AD9249-65EBZ in the default condition. Other VisualAnalog features and capture settings are documented in the AN-905 Application Note, VisualAnalog Converter Evaluation Tool Version 1.0 User Manual.
After the ADC data capture board setup is complete, set up the SPI controller software using the following procedure:
Figure 10. SPI Controller, CHIP ID(1) Box
Figure 11. SPI Controller, New DUT Button
Figure 12. SPI Controller, CLOCK DIVIDE(B) Box
Figure 13. SPI Controller, Chip Power Mode - Digital Reset Selection
Figure 14. SPI Controller, Example ADC A Page
Figure 15. Run/Continuous Run Buttons (Encircled in Red) in VisualAnalog Toolbar, Collapsed Display
The next step is to adjust the amplitude of the input signal for each channel as follows:
Figure 16. Graph Window of VisualAnalog
Lack of SPI communication will cause difficulty in configuring the ADC.
If the FFT plot appears abnormal, do the following:
If the FFT appears normal but the performance is poor, check the following:
If the FFT window remains blank after Run in VisualAnalog (see Figure 15) is clicked, do the following: