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resources:eval:ad9082 [24 Feb 2021 15:37] – updates to PFILT section Umesh Jayamohanresources:eval:ad9082 [24 Feb 2021 17:58] – added section on ADC performance Umesh Jayamohan
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 Below is the spectrum of the DAC output two tones representing the center frequencies of the two bands.  Below is the spectrum of the DAC output two tones representing the center frequencies of the two bands. 
 {{:resources:eval:mxfe:dac_output_dualband.png|DAC outputs showing the center frequencies of the two bands}} {{:resources:eval:mxfe:dac_output_dualband.png|DAC outputs showing the center frequencies of the two bands}}
 +
 +====== A Note on ADC performance =======
 +The AD9081/AD9988/AD9082/AD9986 are highly integrated direct RF transceivers. Hence, the performance of the ADC may vary based on the device setup. For example, if the AD9082-FMCA-EBZ was setup to run in a transceiver mode (with DACs ON), and receive only mode (ADC only), there will be a noticeable difference in the ADC's noise performance. See below:
 +{{:resources:eval:mxfe:ad9082_2p7ghz_adconlyfft.png?600|2.7GHz -1dBFS tone with AD9082 configured as a transceiver}}{{:resources:eval:mxfe:ad9082_2p7ghz_trxmodefft.png?600|2.7GHz -1dBFS tone with AD9082 configured in Rx only mode}}
  
  
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 {{ :resources:eval:mxfe:Figure17.png |FFT plot Channel 1 which is Q channel with Q mode Enabled under PFILT Configuration Tool.   }}  {{ :resources:eval:mxfe:Figure17.png |FFT plot Channel 1 which is Q channel with Q mode Enabled under PFILT Configuration Tool.   }} 
   Figure 17: FFT plot Channel 1 which is Q channel with Q mode Enabled under PFILT Configuration Tool.   Figure 17: FFT plot Channel 1 which is Q channel with Q mode Enabled under PFILT Configuration Tool.
 +
 +======= Troublshooting Tips =======
 + 
 +** Evaluation Board is not Functioning Properly **
 +  * Ensure that the evaluation board is properly seated in the FMC connector
 +  * After ACE has programmed the FPGA, power is provided to the evaluation board. Ensure that the LEDs that denote power is ok, are all lit. See image below. 
 +{{:resources:eval:mxfe:ceboard_power_rail_led.jpg?200|LEDs denoting power to the various rails on the evaluation board}} 
 +
 +  * Ensure that the eRPC server has made a successful connection to the evaluation board. If the Chip Info reads back a successful UID, this means that the connection is successful. Otherwise, the UID will read 0x0 (see Figure 11). If this is the case, power cycle the board, and restart all software. 
 +
 +** ACE is slow to capture data and setup the board **
 +  * Ensure that the USB connection between ADS9-v2EBZ board and the PC is done through a USB3.0 cable. 
 +  * Connect the cable to a USB3.0 supported port on the PC
 +  * Restart all software and hardware
 +
 +** Unable to capture data after device is setup **
 +
 +In some instances, the user may be unable to capture data from the FPGA. This is characterized by no capture via ACE, or a “configure channel failed” error in ACE. In either case, only four of the six LEDs on the FPGA board will be lit (see figure below).
 +
 +{{:resources:eval:mxfe:ads9v2_unsuccessful_capture.jpg?200|LED status on ADS9-v2EBZ following an unsuccessful data capture}}
 +
 +If this happens, and the setup is using an external direct clock to the chip, ensure that the instrumentation is setup as explained in the evaluation board user guide UG-1829. Ensure the correct clock and refclock frequencies are set. Check the connections to the board to make sure they are snug. If the problem persists, open DPG Lite and download a tone. After this step, a successful data capture will show all the LEDs lit. See figure below. 
 +
 +{{:resources:eval:mxfe:ads9v2_successful_capture.jpg?200|LED status on ADS9-v2EBZ following a successful data capture}} 
 +
 +** HMC7044 Configuration Error **
 +
 +When operating with the on-board clocking and on-chip PLL mode, the user can get a “HMC7044 Configuration Error” in the ACE setup. 
 +
 +{{:resources:eval:mxfe:hmc7044_config_error.png?200|HMC7044 Configuration Error (REFCLK value cannot be supported using a 100MHz Crystal Oscillator)}}
 +
 +If this happens, ensure the correct modes are selected to setup the chip. Please note that not all modes that are listed in the UG-1578, device user guide, are supported by the evaluation board hardware using the on-board HMC7044 clock and on-chip PLL. This is because the HMC7044 derives the reference from a 100MHz crystal oscillator if using the FMCA version, or 122.88MHz crystal oscillator if using the FMCB version of the evaluation board. 
 + 
 +If this use case is required, the best approach is to switch to using the direct external clock. This bypasses the HMC7044 setup and the user is not limited to the setup options provided only by the combination of on-board crystal oscillator and the HMC7044 setup. 
 +
resources/eval/ad9082.txt · Last modified: 06 Oct 2022 16:31 by Sydney Wells

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