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resources:eval:ad6674-1000ebz [17 Nov 2022 03:19] – [Equipment Needed] John Xavier Toledo | resources:eval:ad6674-1000ebz [18 Apr 2024 01:54] (current) – 4/18/24 Deferson Romero | ||
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- | The [[adi> | + | The [[adi> |
===== AD6674 Evaluation Board ===== | ===== AD6674 Evaluation Board ===== | ||
{{ : | {{ : | ||
- | // | + | // |
{{ : | {{ : | ||
- | // | + | // |
- | Figure | + | Figure |
- | // | + | // |
===== Typical Measurement Setup ===== | ===== Typical Measurement Setup ===== | ||
The [[adi> | The [[adi> | ||
{{ : | {{ : | ||
- | // | + | // |
</ | </ | ||
{{ : | {{ : | ||
- | // | + | // |
</ | </ | ||
===== Features ===== | ===== Features ===== | ||
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===== Software Needed ===== | ===== Software Needed ===== | ||
- | * [[adi> | + | * [[adi> |
- | * [[adi> | + | ===== Tools ===== |
+ | * [[https:// | ||
+ | * [[https:// | ||
===== Design and Integration Files ===== | ===== Design and Integration Files ===== | ||
* {{: | * {{: | ||
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==== Configuring the Board ==== | ==== Configuring the Board ==== | ||
Before using the software for testing, configure the evaluation board as follows: | Before using the software for testing, configure the evaluation board as follows: | ||
- | - Connect the evaluation board to the [[ads7-v2|ADS7-V2EBZ]]/ | + | - Connect the evaluation board to the [[adi> |
- | - Connect one 12V, 6.5A switching power supply (such as the CENB1080A1251F01 supplied) to P4 on the [[ads7-v2|ADS7-V2EBZ]]/ | + | - Connect one 12V, 6.5A switching power supply (such as the CENB1080A1251F01 supplied) to P4 on the [[adi> |
- | - Turn on the [[ads7-v2|ADS7-V2EBZ]]/ | + | - Turn on the [[adi> |
- | - The [[ads7-v2|ADS7-V2EBZ]]/ | + | - The [[adi> |
- | - If the Device Manager does not show the [[ads7-v2|ADS7-V2EBZ]]/ | + | - If the Device Manager does not show the [[adi> |
- | - On the ADC evaluation board, provide a clean, low jitter | + | - On the ADC evaluation board, provide a clean, low jitter |
- On the ADC evaluation board, provide a clean, low jitter clock source to connector J804 and set the amplitude to 10dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:< | - On the ADC evaluation board, provide a clean, low jitter clock source to connector J804 and set the amplitude to 10dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:< | ||
- On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to P200. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to P200. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, | ||
- On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel B to P202. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel B to P202. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, | ||
- | ==== Visual Analog | + | ==== Software |
+ | <WRAP indent> | ||
+ | < | ||
+ | |||
+ | <hidden ACE Setup> | ||
+ | - Download and install [[adi> | ||
+ | - The AD6674 ACE plug-in can be found under the [[adi> | ||
+ | - Once the .acezip file has been downloaded from the Analog Devices website, right click on it and install the plug-in, or double click to install. | ||
+ | - Click Start -> All Programs -> Analog Devices -> ACE -> ACE | ||
+ | - The AD6674 plug-in should appear as in Figure 5 if installed correctly.< | ||
+ | - If the AD6674 plug-in does not appear, or no board is detected, make sure the ADS7-V2 is powered on and the evaluation board is properly connected. Make sure that ACE has been updated to the most recent version and the necessary plug-ins have been installed.< | ||
+ | - Double click on the plug-in to open it. This will open the AD6674 Board View.< | ||
+ | - Double click on the blue AD6674 chip (in the middle of the board) to open up the Chip View.< | ||
+ | </ | ||
+ | |||
+ | <hidden Visual Analog & SPI Controller Setup> | ||
+ | **Visual Analog Setup** | ||
- Click Start < | - Click Start < | ||
- | - On the VisualAnalog “New Canvas” window, click **ADC**< | + | - On the VisualAnalog “New Canvas” window, click **ADC**< |
- | - At this point, VisualAnalog will automatically detect the evaluation board and the FPGA data capture board and ask if it can program the FPGA with the appropriate bin file. This is shown in figure 6.{{ : | + | - At this point, VisualAnalog will automatically detect the evaluation board and the FPGA data capture board and ask if it can program the FPGA with the appropriate bin file. This is shown in Figure 9.{{ : |
- | - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure | + | - If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure |
- | - Click the **Settings** button in the **ADC Data Capture** block as shown in Figure | + | - Click the **Settings** button in the **ADC Data Capture** block as shown in Figure |
- | - On the **General** tab make sure the clock frequency is set to **1000MHz** (or other clock frequency). The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The ADS7-V2 and ADS7-V1 FPGA software supports up to 2M FFT capture (1M per channel){{ : | + | - On the **General** tab make sure the clock frequency is set to **750MHz** (or other clock frequency). The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The [[adi> |
- | - If the board did not Auto-program click on the **Capture Board** tab and browse to the **ad9680_ads7v1.bin** or the **ad9680_ads7v2.bin** file depending on which data capture board is being used. Click the **Program** button. The **FPGA_DONE** LED should illuminate on the ADS7-V1 board indicating that the FPGA has been correctly programmed. | + | - If the board did not Auto-program click on the **Capture Board** tab and browse to the **ad9680_ads7v1.bin** or the **ad9680_ads7v2.bin** file depending on which data capture board is being used. Click the **Program** button. The **FPGA_DONE** LED should illuminate on the [[adi> |
- On the **Device** tab. Make sure that **Enable Alternate REFCLK** option is unchecked. | - On the **Device** tab. Make sure that **Enable Alternate REFCLK** option is unchecked. | ||
- Click **OK** | - Click **OK** | ||
- | ==== SPIController | + | **SPI Controller |
- Click Start < | - Click Start < | ||
- Select the appropriate configuration file when prompted. | - Select the appropriate configuration file when prompted. | ||
- | - In the **Global** tab, under the **Generic Read/ | + | - In the **Global** tab, under the **Generic Read/ |
- | - The JESD204B quick configuration and Lane Rate registers are available in the **ADCBase3** tab. Set the Lane Rate setting register 0x56E to **Low Lane Rate Mode**{{ : | + | - The JESD204B quick configuration and Lane Rate registers are available in the **ADCBase3** tab. Set the Lane Rate setting register 0x56E to **Low Lane Rate Mode**{{ : |
- | - Set the JESD204B Quick Configuration register 0x570. For 1000MSPS operation with with default conditions (//Noise Shaped Requantizer (NSR) Mode//), the values for **L.M.F** are **4.2.1**{{ : | + | - Set the JESD204B Quick Configuration register 0x570. For 1000MSPS operation with with default conditions (//Noise Shaped Requantizer (NSR) Mode//), the values for **L.M.F** are **4.2.1**{{ : |
- After the quick configuration setting is completed, the PLL Lock Detect register 0x56F will read 0x80 to denote a lock. The SPIController interface will show a " | - After the quick configuration setting is completed, the PLL Lock Detect register 0x56F will read 0x80 to denote a lock. The SPIController interface will show a " | ||
- Toggle the JESD204B link by checking and then unchecking the **JESD204B Serial Transmit Power Down** box | - Toggle the JESD204B link by checking and then unchecking the **JESD204B Serial Transmit Power Down** box | ||
- | - Individual Channel control for **ADC A** and **ADC B** are done using the Device Index Register (0x008) in the Global tab.{{ : | + | - Individual Channel control for **ADC A** and **ADC B** are done using the Device Index Register (0x008) in the Global tab.{{ : |
- Under **ADC A** and **ADC B** tabs the options for Channel A and B are listed. Default settings have been programmed to ensure optimal performance for the input bandwidth and sample rate. Only the following options need to be operated with: | - Under **ADC A** and **ADC B** tabs the options for Channel A and B are listed. Default settings have been programmed to ensure optimal performance for the input bandwidth and sample rate. Only the following options need to be operated with: | ||
- Chip Configuration Register (2): This option allows the channel to be powered on | - Chip Configuration Register (2): This option allows the channel to be powered on | ||
Line 99: | Line 117: | ||
- Analog Input Differential Termination (16): This sets the input termination. Recommended settings are 500, 200, 100, 50 ohms. At lower termination settings, the harmonic distortion performance may show improvement, | - Analog Input Differential Termination (16): This sets the input termination. Recommended settings are 500, 200, 100, 50 ohms. At lower termination settings, the harmonic distortion performance may show improvement, | ||
- Input Full Scale Range (25): At high input frequencies, | - Input Full Scale Range (25): At high input frequencies, | ||
- | ==== Device Setup - NSR Mode ==== | + | </ |
- | | + | |
- | - The NSR mode settings are configured in the ADCA and ADCB tabs. The NSR defaults to 21% bandwidth mode with a tuning word of 0. Decimate by 2 is enabled by default also on the AD6674-750 and AD6674-1000 (and cannot be disabled in NSR mode).{{ : | + | ==== Sample Configuration 1: NSR Mode ==== |
- | ==== Obtaining an FFT - NSR Mode ==== | + | The default Chip Application Mode for the AD6674-750/ |
- | - The first item to configure in Visual Analog is the input clock frequency. | + | <hidden ACE Configuration> |
- | - In order to obtain an FFT with NSR enabled, Visual Analog must be configured correctly. | + | - Under **Initial Configuration** at board view, set the following configuration below: |
+ | * Clock input: **750 MHz** | ||
+ | * Decimate/2: **True** | ||
+ | * Bandwidth Mode: **21%** | ||
+ | * Lane (L): **4** | ||
+ | * Virtual Converter (M): **2** | ||
+ | * Octets per Frame (F): **1** | ||
+ | * Bits per Sample (N'): **16**< | ||
+ | - Click **Apply** to apply the chip settings. Set the **reference clock** to **187.5 MHz** to match these settings and click AD6674 to be directed to chip view.< | ||
+ | - Click **Apply** at **AD6674 Configuration**, | ||
+ | - Issue a **Data Path Reset** to the AD6674 by clicking its checkbox and then **Apply Changes**. The data path reset bit will automatically self-clear.{{ : | ||
+ | - If the **PLL Locked** indicator lights up, you can reset it by powering down the JESD link using the **Link Control** dropdown box, and clicking **Apply Changes**.{{ : | ||
+ | - Enable the **Link Control** again and **Apply Changes**.{{ : | ||
+ | - Click **Proceed to Analysis**. This is ACE's Analysis tool for the data from the ADC, displaying both sample plots (Waveform) and FFTs. Click on **FFT** and **Run Once** to capture once.{{ : | ||
+ | - **Channel A** and **Channel B** can be selected individually to display their **FFTs**. A successful capture is shown below, with a 75 MHz signal inputted at on both Channel A and B. Adjust the amplitude of the input signal so that the fundamental is at the desired level. NSR imposes a ~3dB loss in the signal but does not impact the dynamic range. A -1.0 dBFS input signal will show as -4.0 dBFS in the FFT.{{ : | ||
+ | - To save the FFT plot, click on **Export** button at **Analysis Results** tab and save it to a location of choice. | ||
+ | </ | ||
+ | <hidden Visual Analog & SPI Controller Configuration> | ||
+ | **SPI Controller Configuration** | ||
+ | <WRAP centeralign> | ||
+ | - The NSR mode settings are configured in the ADCA and ADCB tabs. The NSR defaults to 21% bandwidth mode with a tuning word of 0. Decimate by 2 is enabled by default also on the AD6674-750 and AD6674-1000 (and cannot be disabled in NSR mode).{{ : | ||
+ | **Visual Analog Configuration** | ||
+ | - The first item to configure in Visual Analog is the input clock frequency. | ||
+ | - In order to obtain an FFT with NSR enabled, Visual Analog must be configured correctly. | ||
- In this example, with an input clock of 750MHz, the output sample rate is 375MSPS. | - In this example, with an input clock of 750MHz, the output sample rate is 375MSPS. | ||
- | - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ : | + | - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ : |
- Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) NSR imposes a ~3dB loss in the signal, but does not impact the dynamic range. | - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) NSR imposes a ~3dB loss in the signal, but does not impact the dynamic range. | ||
- To save the FFT plot do the following | - To save the FFT plot do the following | ||
- | - Click on the Float Form button in the FFT window{{ : | + | - Click on the Float Form button in the FFT window{{ : |
- | - Click on File < | + | - Click on File < |
+ | </hidden> | ||
- | ==== Device Setup - VDR Mode ==== | + | ==== Sample Configuration 2: VDR Mode ==== |
- | - The default | + | <hidden ACE Configuration> |
- | - The VDR mode tuning word can be configured in the ADC A and ADC B tabs. VDR defaults to 25% bandwidth complex mode with a tuning word of 0. The tuning word can be changed using the VDR Tuner Frequency selection (register 0x434). | + | |
- | - Using the default lane configuration in the AD6674 (L.M.F = 4.2.1) the JESD204B lane rate will be 7.5 Gbps which means the PLL must be set to Maximum Lane Rate Mode (0x56E) int he ADCBase3 tab in SPIController. {{ : | + | * Clock input: **750 MHz** |
- | ==== Obtaining an FFT - VDR Mode ==== | + | * Chip Operating |
- | - The first item to configure in Visual Analog is the input clock frequency. | + | * Complex Enabled: **Dual Complex Mode** |
+ | * Bandwidth Mode: **25%** | ||
+ | * Lane (L): **4** | ||
+ | * Virtual Converter (M): **2** | ||
+ | * Octets per Frame (F): **1** | ||
+ | * Bits per Sample (N'): **16**< | ||
+ | - Click **Apply** to apply the chip settings. Set the **reference clock** to **375 MHz** to match these settings and click AD6674 | ||
+ | | ||
+ | - Issue a **Data Path Reset** to the AD6674 | ||
+ | - If the **PLL Locked** indicator lights up, you can reset it by powering down the JESD link using the **Link Control** dropdown box, and clicking **Apply Changes**.{{ : | ||
+ | - Enable the **Link Control** again and **Apply Changes**.{{ : | ||
+ | - Click **Proceed to Analysis**. This is ACE's Analysis tool for the data from the ADC, displaying both sample plots (Waveform) and FFTs. Click on **FFT** and **Run Once** to capture once.{{ : | ||
+ | - **Channel A** and **Channel B** can be selected individually to display their **FFTs**. A successful capture is shown below, | ||
+ | - To save the FFT plot, click on **Export** button at **Analysis Results** tab and save it to a location of choice. | ||
+ | </ | ||
+ | <hidden Visual Analog & SPI Controller Configuration> | ||
+ | **SPI Controller Configuration** | ||
+ | - The settings in the ADCBase0 tab must be changed to configure the AD6674 into VDR mode. To set up the AD6674 for VDR mode change the Chip Application Mode in register 0x200 to Variable Dynamic Range (VDR) Mode and set the Chip Decimation Ratio in register 0x201 to Full Sample Rate. {{ : | ||
+ | - The VDR mode tuning word can be configured in the ADC A and ADC B tabs. VDR defaults to 25% bandwidth complex mode with a tuning word of 0. The tuning word can be changed using the VDR Tuner Frequency selection (register 0x434). | ||
+ | - Using the default lane configuration in the AD6674 (L.M.F = 4.2.1) the JESD204B lane rate will be 7.5 Gbps which means the PLL must be set to Maximum Lane Rate Mode (0x56E) int he ADCBase3 tab in SPIController. {{ : | ||
+ | **Visual Analog Configuration** | ||
+ | - The first item to configure in Visual Analog is the input clock frequency. | ||
- In this example, with an input clock of 750MHz, the output sample rate is 750MSPS. | - In this example, with an input clock of 750MHz, the output sample rate is 750MSPS. | ||
- | - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ : | + | - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ : |
- Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) VDR imposes no loss on the input signal so a -1.0 dBFS input signal will show as -1.0 dBFS in the FFT in Visual Analog. | - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) VDR imposes no loss on the input signal so a -1.0 dBFS input signal will show as -1.0 dBFS in the FFT in Visual Analog. | ||
- To save the FFT plot do the following | - To save the FFT plot do the following | ||
- | - Click on the Float Form button in the FFT window{{ : | + | - Click on the Float Form button in the FFT window{{ : |
- | - Click on File < | + | - Click on File < |
- | ==== Setting up SPIController to Use Control Bits as VDR Punish Bits and the VDR High/Low Resolution Bit - VDR Mode ==== | + | </ |
- | - The first step go to the ADCBase2 tab in SPIController to set up the control bits to select the VDR indicator bits. In this example Control Bit 2 is set to VDR Punish Bit 1, Control Bit 1 is set to VDR Punish Bit 0, and Control Bit 0 is set to the VDR High/Low resolution bit. (Similarly, the control bits may be set up to function as Overrange, Signal Monitor (SMON), | + | |
- | - Next go to the ADCBase4 tab to set up the control bits to select the VDR indicator bits. In this example three control bits are sent per sample. In order to accommodate three control bits, the converter resolution (N) must be set to 13 bits (there are 16 available bits in the JESD204B data word and if three are used for control bits there are 13 bits available for the converter sample - in this example this means there will only be 13 bits available instead of the 14 bits of converter resolution.{{ : | + | ==== Sample Configuration 2.1: VDR Mode - Use Control Bits as VDR Punish Bits and the VDR High/Low Resolution Bit ==== |
- | ==== Viewing the VDR Punish Bits and the VDR High/Low Resolution Bit - VDR Mode ==== | + | <note tip> |
- | - The first step is to open a new Logic canvas in VisualAnalog. | + | <hidden Visual Analog & SPI Controller Configuration> |
- | - Next configure the Logic Analysis block for the data alignement. | + | **SPI Controller Configuration** |
- | - These settings will create the space in the Logic Canvas display so that all three control bits available in the JESD204B data stream will be visible. (While the example here is for VDR the control bits may be set up to function as Overrange, Signal Monitor (SMON), or Fast Detect (FD) indicators and can be viewed in the output data in a similar manner.) {{ : | + | - The first step, go to the ADCBase2 tab in SPIController to set up the control bits to select the VDR indicator bits. In this example Control Bit 2 is set to VDR Punish Bit 1, Control Bit 1 is set to VDR Punish Bit 0, and Control Bit 0 is set to the VDR High/Low resolution bit. (Similarly, the control bits may be set up to function as Overrange, Signal Monitor (SMON), |
- | - Once a signal is input that will trigger VDR to operate the VDR punish bits [1:0] and the VDR High/Low resolution bit can be seen in the Logic Canvas display. In this case control bit 2 is VDR punish bit 1, control bit 1 is VDR punish bit 0, and control bit 0 is the VDR High/Low resolution bit. {{ : | + | - Next go to the ADCBase4 tab to set up the control bits to select the VDR indicator bits. In this example three control bits are sent per sample. In order to accommodate three control bits, the converter resolution (N) must be set to 13 bits (there are 16 available bits in the JESD204B data word and if three are used for control bits there are 13 bits available for the converter sample - in this example this means there will only be 13 bits available instead of the 14 bits of converter resolution.{{ : |
- | - Note that the data alignment from the FPGA to VisualAnalog will fill in the control bits starting from the LSB location in the Logic Canvas display. | + | **Visual Analog Configuration** |
- | ==== Device Setup - 2 ADCs, 2DDCs, Real Mode Decimate by 2 ==== | + | - The first step is to open a new Logic canvas in VisualAnalog. |
- | - The default | + | - Next configure the Logic Analysis block for the data alignement. |
+ | - These settings will create the space in the Logic Canvas display so that all three control bits available in the JESD204B data stream will be visible. (While the example here is for VDR the control bits may be set up to function as Overrange, Signal Monitor (SMON), or Fast Detect (FD) indicators and can be viewed in the output data in a similar manner.) {{ : | ||
+ | - Once a signal is input that will trigger VDR to operate the VDR punish bits [1:0] and the VDR High/Low resolution bit can be seen in the Logic Canvas display. In this case control bit 2 is VDR punish bit 1, control bit 1 is VDR punish bit 0, and control bit 0 is the VDR High/Low resolution bit. {{ : | ||
+ | - Note that the data alignment from the FPGA to VisualAnalog will fill in the control bits starting from the LSB location in the Logic Canvas display. | ||
+ | </ | ||
+ | |||
+ | ==== Sample Configuration 3: 2 ADCs, 2DDCs, Real Mode Decimate by 2 ==== | ||
+ | <hidden ACE Configuration> | ||
+ | | ||
+ | * Clock input: **750 MHz** | ||
+ | * Chip Operating | ||
+ | * DDC 0 and DDC 1 I/Q Input Select: **Channel A** | ||
+ | * DDC 0 and DDC 1 Decimation Ratio: **HB1_HB2** | ||
+ | * DDC 0 and DDC 1 Output Select: **Real(I) Output Only.** | ||
+ | * Lane (L): **4** | ||
+ | * Virtual Converter (M): **2** | ||
+ | * Octets per Frame (F): **1** | ||
+ | * Bits per Sample (N'): **16**< | ||
+ | - Click **Apply** to apply the chip settings. Set the **reference clock** to **187.5 MHz** to match these settings and click AD6674 | ||
+ | | ||
+ | - NCO Frequency: **93.75 MHz** | ||
+ | - IF Mode: **Variable IF Mode** | ||
+ | - Gain Select: **6 dB** | ||
+ | - Mixer Select: **Real Mixer** | ||
+ | - Click **Apply** at **AD6674 Configuration**. Then chip view will update to reflect all the changes made. If any changes are made, the chip can be read by clicking the **Read All button**.{{ : | ||
+ | - After applying DDC settings, set **DDC Soft Reset** to **DDC Held in Reset** and **Apply Changes**, then return it back to **Normal Operation** and **Apply Changes**.{{ : | ||
+ | - Issue a **Data Path Reset** to the AD6674 | ||
+ | - If the **PLL Locked** indicator lights up, you can reset it by powering down the JESD link using the **Link Control** dropdown box, and clicking **Apply Changes**.{{ : | ||
+ | - Enable the **Link Control** again and **Apply Changes**.{{ : | ||
+ | - Click **Proceed to Analysis**. This is ACE's Analysis tool for the data from the ADC, displaying both sample plots (Waveform) and FFTs. Click on **FFT** and **Run Once** to capture once.{{ : | ||
+ | - **Channel A** and **Channel B** can be selected individually to display their **FFTs**. A successful capture is shown below, | ||
+ | - To save the FFT plot, click on **Export** button at **Analysis Results** tab and save it to a location of choice. | ||
+ | </ | ||
+ | <hidden Visual Analog & SPI Controller Configuration> | ||
+ | **SPI Controller Configuration** | ||
+ | - The settings in the ADCBase0 tab must be changed to configure the AD6674 to use the DDCs. In this example the AD6674 is set up to use two DDCs (one per ADC channel) with real outputs and a decimation ratio of two. Set the Chip Application Mode in register 0x200 to Two Digital Down Converters and select the Only Real (I) Selected checkbox. | ||
- The DDC settings must be configured in ADCBase1, but first, the tuning step, translation frequency, and DDC Phase Increment must be calculated. | - The DDC settings must be configured in ADCBase1, but first, the tuning step, translation frequency, and DDC Phase Increment must be calculated. | ||
- The tuning step is equal to the output sample rate divided by 4096. | - The tuning step is equal to the output sample rate divided by 4096. | ||
Line 143: | Line 241: | ||
- DDC Phase Increment = 46875000/ | - DDC Phase Increment = 46875000/ | ||
- Under DDCO CTRL and DDC1 CTRL in the ADCBase1 tab configure the DDCs to select 6dB Gain, Variable IF Mode, Real(I) Decimate by 2 Filter Selection, Both Input Sample Selections to Channel A for DDC0 and Channel B for DDC1, and the DDC Phase Increment to the calculated value of 512 | - Under DDCO CTRL and DDC1 CTRL in the ADCBase1 tab configure the DDCs to select 6dB Gain, Variable IF Mode, Real(I) Decimate by 2 Filter Selection, Both Input Sample Selections to Channel A for DDC0 and Channel B for DDC1, and the DDC Phase Increment to the calculated value of 512 | ||
- | - After changing DDC selections, perform a soft reset of the DDCs by checking and unchecking the box for DDC Soft Reset under the DDC Synchronization CTRL Reg (300). {{ : | + | - After changing DDC selections, perform a soft reset of the DDCs by checking and unchecking the box for DDC Soft Reset under the DDC Synchronization CTRL Reg (300). {{ : |
- Using the default lane configuration in the AD6674 (L.M.F = 4.2.1) the JESD204B lane rate will be 3.75Gbps which means that the PLL needs to be set to Low Lane Rate Mode (0x56E) in the ADCBase3 tab in SPIController. This is the default setting so no change is needed. | - Using the default lane configuration in the AD6674 (L.M.F = 4.2.1) the JESD204B lane rate will be 3.75Gbps which means that the PLL needs to be set to Low Lane Rate Mode (0x56E) in the ADCBase3 tab in SPIController. This is the default setting so no change is needed. | ||
- | ==== Obtaining an FFT - 2 ADCs, 2DDCs, Real Mode Decimate by 2 ==== | + | **Visual Analog Configuration** |
- | - 1. The first item to configure in Visual Analog is the input clock frequency. | + | - The first item to configure in Visual Analog is the input clock frequency. |
- In this example, with an input clock of 750MHz, the output sample rate is 375MSPS. | - In this example, with an input clock of 750MHz, the output sample rate is 375MSPS. | ||
- | - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ : | + | - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ : |
- Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) Real DDC operation imposes ~0.7 dB loss on the input signal but does not impact the dynamic range. | - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) Real DDC operation imposes ~0.7 dB loss on the input signal but does not impact the dynamic range. | ||
- To save the FFT plot do the following | - To save the FFT plot do the following | ||
- | - Click on the Float Form button in the FFT window{{ : | + | - Click on the Float Form button in the FFT window{{ : |
- | - Click on File < | + | - Click on File < |
- | ==== Device Setup - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2 ==== | + | </ |
- | - The default Chip Application Mode for the AD6674 is Noise Shaped Requantizer (NSR) Mode with the Chip Decimation Ratio of 2 (decimation is disabled on the AD6674-500). | + | |
+ | ==== Sample Configuration 4: 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2 ==== | ||
+ | <hidden Visual Analog & SPI Controller Configuration> | ||
+ | **SPI Controller Configuration** | ||
+ | - The settings in the ADCBase0 tab must be changed to configure the AD6674 to use the DDC. In this example the AD6674 will be set up to use one DDCs with a complex ZIF output (NCO bypassed) and a decimation ration of two. Set the Chip Application Mode in register 0x200 to One Digital Down Converter and make sure the Only Real (I) Selected checkbox is **//NOT//** checked. | ||
- The DDC settings must be configured under DDCO CTRL in the ADCBase1 tab configure the DDC to select Complex Mixer Selection, 0 Hz IF Mode, Decimate by 2 Filter Selection, Real (I) Input Sample Selection to Channel A for DDC0, and Complex (Q) Input Sample Selection to Channel B. | - The DDC settings must be configured under DDCO CTRL in the ADCBase1 tab configure the DDC to select Complex Mixer Selection, 0 Hz IF Mode, Decimate by 2 Filter Selection, Real (I) Input Sample Selection to Channel A for DDC0, and Complex (Q) Input Sample Selection to Channel B. | ||
- After changing DDC selections, perform a soft reset of the DDCs by checking and unchecking the box for DDC Soft Reset under the DDC Synchronization CTRL Reg (300). {{ : | - After changing DDC selections, perform a soft reset of the DDCs by checking and unchecking the box for DDC Soft Reset under the DDC Synchronization CTRL Reg (300). {{ : | ||
- Using the default lane configuration in the AD6674 (L.M.F = 4.2.1) the JESD204B lane rate will be 3.75Gbps which means that the PLL needs to be set to Low Lane Rate Mode (0x56E) in the ADCBase3 tab in SPIController. This is the default setting so no change is needed. | - Using the default lane configuration in the AD6674 (L.M.F = 4.2.1) the JESD204B lane rate will be 3.75Gbps which means that the PLL needs to be set to Low Lane Rate Mode (0x56E) in the ADCBase3 tab in SPIController. This is the default setting so no change is needed. | ||
- | ==== Obtaining an FFT - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2 ==== | + | **Visual Analog Configuration** |
- | - The first item to configure in Visual Analog is the input clock frequency. | + | - The first item to configure in Visual Analog is the input clock frequency. |
- In this example, with an input clock of 750MHz, the output sample rate is 750MSPS. | - In this example, with an input clock of 750MHz, the output sample rate is 750MSPS. | ||
- | - In order to exclude the image frequency from the SFDR measurements, | + | - In order to exclude the image frequency from the SFDR measurements, |
- | - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ : | + | - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ : |
- Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the “Fund Power” reading in the left panel of the VisualAnalog FFT window.) Complex DDC operation imposes ~1dB loss in the signal, but does not impact the dynamic range. | - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the “Fund Power” reading in the left panel of the VisualAnalog FFT window.) Complex DDC operation imposes ~1dB loss in the signal, but does not impact the dynamic range. | ||
- To save the FFT plot do the following | - To save the FFT plot do the following | ||
- | - Click on the Float Form button in the FFT window{{ : | + | - Click on the Float Form button in the FFT window{{ : |
- | - Click on File < | + | - Click on File < |
+ | </ | ||
===== Troubleshooting Tips ===== | ===== Troubleshooting Tips ===== | ||
+ | ** Evaluation board is not functioning properly ** | ||
+ | * It is possible that a board component has been rendered inoperable by ESD, accidental shorting while probing, etc. Try checking the supply domain voltages of the board while it is powered. They should be as follows: | ||
+ | *< | ||
+ | ^ Domain | ||
+ | | AVDD_1 | ||
+ | | AVDD_1 | ||
+ | | AVDD_2 | ||
+ | | AVDD_1P8 | ||
+ | | DVDD | TP407 | 1.25 V | | ||
+ | | DRVDD | ||
+ | </ | ||
+ | * If a short is detected between any of the supply domains and ground, or an open is detected across fuse chip F400 or F401, a component may have been damaged. | ||
+ | |||
+ | ** Evaluation board is not communicating with the ADS7-V2 / No SPI communication ** | ||
+ | * Make sure that the FPGA on the ADS7-V2 has been programmed - a lit LED DS15 (**FPGA_DONE**) on the top of the ADS7-V2 and a powered fan are good indicators of the FPGA being programmed. | ||
+ | * Check the common mode voltage on the JESD204B traces. On the evaluation board, the common mode voltage should be roughly two-thirds of DRVDD_1. On the ADS7-V2, the common mode voltage should be around 1.2 volts. | ||
+ | * To test SPI operation, attempt to both read and write to register 0x00A (Scratch Pad) using ACE's Register Debugger (Tools -> Register Debugger). This register is an open register available for testing memory reads and writes. If the register reads back the same value written to it, SPI is operational. | ||
+ | * All registers reading back as either all ones or all zeros (i.e., 0xFF or 0x00) may indicate no SPI communication. | ||
+ | * Register 0x000 (SPI Configuration A) reading back 0x81 in ACE may indicate no SPI communication as a result of the FPGA on the ADS7-V2 not being programmed. | ||
+ | |||
+ | ** ACE software fails to capture date ** | ||
+ | * Ensure that the board is functioning properly and that SPI communication is successful - see previous troubleshooting tips. | ||
+ | * Check the Clock Status register 0x011C to see if the input sample clock is being detected. 0x01 indicates detection, 0x00 indicates no clock detected. Check the signal generator input on connector J801. Try checking the common mode voltage on the clock pins, which should be roughly two-thirds of AVDD_1. Try placing a differential oscilloscope probe on the clock pins to see if the clock signal is reaching the chip. | ||
+ | * Check the PLL Locked indicator (see figure 23) or register 0x056F (PLL Status). If the light in the plugin chip view is green or if the register reads back 0x80, the PLL is locked. If it is not locked: | ||
+ | * Check the clock being input to connector J801. | ||
+ | * Check the JESD204B settings under the Initial Configuration. Reference the [[adi> | ||
+ | * Check the Reference Clock and make sure it matches your JESD settings. | ||
+ | * Make sure P100 (Power Down / Standby Jumper) is not jumped. | ||
** FFT plot appears abnormal ** | ** FFT plot appears abnormal ** | ||
* If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure you are not overdriving the ADC. Reduce input level if necessary. | * If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure you are not overdriving the ADC. Reduce input level if necessary. | ||
* In VisualAnalog, | * In VisualAnalog, | ||
- | * Issue a **Data Path Soft Reset** | + | * Issue a **Data Path Soft Reset** |
** The FFT plot appears normal, but performance is poor. ** | ** The FFT plot appears normal, but performance is poor. ** | ||
Line 182: | Line 312: | ||
** The FFT window remains blank after the Run button is clicked ** | ** The FFT window remains blank after the Run button is clicked ** | ||
- | * Make sure the evaluation board is securely connected to the ADS7-V1. | + | * Make sure the evaluation board is securely connected to the [[adi> |
- | * Make sure the FPGA has been programmed by verifying that the **Config DONE** LED is illuminated on the ADS7-V1. If this LED is not illuminated reprogram the FPGA through VisualAnalog. If the LED still does not illuminate disconnect the USB and power cord for 15 seconds. Connect again and repeat the ADS7-V1 setup process. | + | * Make sure the FPGA has been programmed by verifying that the **Config DONE** LED is illuminated on the [[adi> |
* Make sure the correct FPGA //bin// file was used to program the FPGA. | * Make sure the correct FPGA //bin// file was used to program the FPGA. | ||
- | * Be sure that the correct sample rate is programmed. Click on the **Settings** button in the **ADC Data Capture** block in VisualAnalog, | ||
* Ensure that the REFCLOCK is ON and set to the appropriate frequency. | * Ensure that the REFCLOCK is ON and set to the appropriate frequency. | ||
- | * Restart SPIController. | + | * Ensure that JESD204B Configuration is correct and the Lane Line Rate is within PLL Range. |
+ | * Ensure that the ADC's PLL is locked by checking the status of the PLL lock detect register **0x56F**. | ||
+ | * In VisualAnalog, | ||
** VisualAnalog indicates that the “FIFO capture timed out” or "FIFO not ready for read back" ** | ** VisualAnalog indicates that the “FIFO capture timed out” or "FIFO not ready for read back" ** | ||
* Make sure all power and USB connections are secure. | * Make sure all power and USB connections are secure. | ||
+ | * Ensure that JESD204B Configuration is within PLL Range and is on PLL Locked. | ||
* Make sure that the REFCLOCK is ON and set to the appropriate frequency. | * Make sure that the REFCLOCK is ON and set to the appropriate frequency. | ||
** VisualAnalog displays a blank FFT when the RUN button is clicked ** | ** VisualAnalog displays a blank FFT when the RUN button is clicked ** | ||
- | * Ensure that the clock to the ADC is supplied. | + | * Ensure that the clock to the ADC is supplied. |
- | * Ensure that the ADC's PLL is locked by checking the status of the PLL lock detect register 0x56F. | + | * Ensure that the ADC's PLL is locked by checking the status of the PLL lock detect register |