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This version (19 Aug 2015 17:38) was approved by J.Harris.The Previously approved version (03 Jun 2015 19:18) is available.Diff

EVALUATING THE AD6674 IF DIVERSITY RECEIVER

Preface

This user guide describes the AD6674 evaluation board AD6674-1000EBZ which provides all of the support circuitry required to operate the ADC in its various modes and configurations. The application software used to interface with the devices is also described. The user guide wiki applies to the follow evaluation boards:

Evaluation Board Part Number Description Board Revision
AD6674-1000EBZ Evaluation board for AD6674-1000; Full Bandwidth 9680CE04B
AD6674-750EBZ Evaluation board for AD6674-750; Full Bandwidth 9680CE04B
AD6674-500EBZ Evaluation board for AD6674-500; Full Bandwidth 9680CE04B
AD6674-LF1000EBZ Evaluation board for AD6674-1000; up to 1GHz Input Bandwidth 9680CE02B
AD6674-LF750EBZ Evaluation board for AD6674-750; up to 1GHz Input Bandwidth 9680CE02B
AD6674-LF500EBZ Evaluation board for AD6674-500; up to 1GHz Input Bandwidth 9680CE02B



The AD6674 data sheet provides additional information and should be consulted when using the evaluation board. All documents and software tools are available at www.analog.com/hsadcevalboard. For additional information or questions, send an email to highspeed.converters@analog.com.

AD6674 Evaluation Board

Figure 1. AD6674 Evaluation Board for full 2GHz Input Bandwidth

Figure 2. AD6674 Low Frequency Evaluation Board up to 1GHz Input Bandwidth

Figure 3 below compares the bandwidth available on the AD6674 normal evaluation boards and the “LF” boards

Figure 3. Comparison of Bandwidth on the Normal and the “LF” boards

Typical Measurement Setup

The AD6674-1000EBZ can be evaluated using the ADS7-V1EBZ or ADS7-V2EBZ FPGA data capture boards. Figures 3 and 4 below show the AD6674-1000EBZ connected to the ADS7-V1EBZ and ADS7-V2EBZ respectively.

Figure 3. Evaluation Board Connection—AD6674-1000EBZ (on Left) and ADS7-V1EBZ (on Right)

Figure 4. Evaluation Board Connection—AD6674-LF1000EBZ (on Left) and ADS7-V2EBZ (on Right)

Features

  • Full featured evaluation board for the AD6674
  • SPI interface for setup and control
  • Wide band Balun driven input
  • No external supply needed. Uses 12V-1A and 3.3V-3A supplies from FMC
  • VisualAnalog® and SPI controller software interfaces

Helpful Documents

Software Needed

Design and Integration Files

Equipment Needed

  • Analog signal source and antialiasing filter
  • Sample clock source
  • 12V, 6.5A switching power supply (such as the SL POWER CENB1080A1251F01 supplied with ADS7-V2EBZ/ADS7-V1EBZ)
  • PC running Windows®
  • USB 2.0 port
  • ADS7-V2EBZ FPGA-based data capture kit, or ADS7-V1EBZ FPGA-based data capture kit

Getting Started

This section provides quick start procedures for using the evaluation board for AD6674.

Configuring the Board

Before using the software for testing, configure the evaluation board as follows:

  1. Connect the evaluation board to the ADS7-V2EBZ/ADS7-V1EBZ data capture board, as shown in Figure 2.
  2. Connect one 12V, 6.5A switching power supply (such as the CENB1080A1251F01 supplied) to P4 on the ADS7-V2EBZ/ADS7-V1EBZ board. Connect the Standard-B USB port of the ADS7-V2EBZ/ADS7-V1EBZ board to the PC with the supplied USB cable.
  3. Turn on the ADS7-V2EBZ/ADS7-V1EBZ.
  4. The ADS7-V2EBZ/ADS7-V1EBZ will appear in the Device Manager.

    Figure 4. Device Manager showing ADS7-V2EBZ/ADS7-V1EBZ

  5. If the Device Manager does not show the ADS7-V2EBZ/ADS7-V1EBZ listed, unplug all USB devices from the PC, uninstall and re-install SPIController and VisualAnalog and restart the hardware setup from step 1.
  6. On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector J801 and set the amplitude to 14dBm. This is the ADC Sample Clock.
  7. On the ADC evaluation board, provide a clean, low jitter clock source to connector J804 and set the amplitude to 10dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:

    LaneLineRate=M*Nprime*(10/8)*f_{out}/Lbps/lane, where

    f_{out} = f_{ADC SAMPLE CLOCK}/DecimationRatio, Nprime=8 or 16(Default Nprime = 16)

    REFCLK = LaneLineRate/20

  8. On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to P200. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.)
  9. On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel B to P202. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.)

Visual Analog Setup

  1. Click Start right All Programs right Analog Devices right VisualAnalog right VisualAnalog
  2. On the VisualAnalog “New Canvas” window, click ADCrightDualrightAD6674

    Figure 5. Selecting the AD6674 canvas

  3. At this point, VisualAnalog will automatically detect the evaluation board and the FPGA data capture board and ask if it can program the FPGA with the appropriate bin file. This is shown in figure 6.

    Figure 6. Programming the ADS7-V2EBZ

  4. If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 5)

    Figure 7. Expanding Display in VA

  5. Click the Settings button in the ADC Data Capture block as shown in Figure 8

    Figure 8. Changing the ADC Capture Settings

  6. On the General tab make sure the clock frequency is set to 1000MHz (or other clock frequency). The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The ADS7-V2 and ADS7-V1 FPGA software supports up to 2M FFT capture (1M per channel)

    Figure 9. Setting the clock frequency and Capture length

  7. If the board did not Auto-program click on the Capture Board tab and browse to the ad9680_ads7v1.bin or the ad9680_ads7v2.bin file depending on which data capture board is being used. Click the Program button. The FPGA_DONE LED should illuminate on the ADS7-V1 board indicating that the FPGA has been correctly programmed.
  8. On the Device tab. Make sure that Enable Alternate REFCLK option is unchecked.
  9. Click OK

SPIController Setup

  1. Click Start right All Programs right Analog Devices right SPIController right SPIController
  2. Select the appropriate configuration file when prompted.
  3. In the Global tab, under the Generic Read/Write section, write 0x81 to register 0x000. This issues a Soft reset for the DUT.

    Figure 10. Sending a Soft Reset to the AD6674

  4. The JESD204B quick configuration and Lane Rate registers are available in the ADCBase3 tab. Set the Lane Rate setting register 0x56E to Low Lane Rate Mode

    Figure 11. Setting the JESD204B Lane Rate

  5. Set the JESD204B Quick Configuration register 0x570. For 1000MSPS operation with with default conditions (Noise Shaped Requantizer (NSR) Mode), the values for L.M.F are 4.2.1

    Figure 12. Setting the JESD204B Quick Configuration Register

  6. After the quick configuration setting is completed, the PLL Lock Detect register 0x56F will read 0x80 to denote a lock. The SPIController interface will show a “1” to denote a lock.
  7. Toggle the JESD204B link by checking and then unchecking the JESD204B Serial Transmit Power Down box
  8. Individual Channel control for ADC A and ADC B are done using the Device Index Register (0x008) in the Global tab.

    Figure 13. Device Index for ADC Channel A and Channel B

  9. Under ADC A and ADC B tabs the options for Channel A and B are listed. Default settings have been programmed to ensure optimal performance for the input bandwidth and sample rate. Only the following options need to be operated with:
    1. Chip Configuration Register (2): This option allows the channel to be powered on
    2. Buffer Current Setting (18): This option allows the buffer current to change to enable better harmonic performance at different frequencies. At high analog input frequencies, the buffer current may need to be increased to optimize harmonic distortion performance (HD2, HD3). Keep in mind that at high frequencies, the performance is also jitter limited. So increasing the buffer currents may lead to diminishing returns with higher power consumption. Refer to the datasheet to understand the relationship between IAVDD3 and Buffer Current Setting.
    3. Analog Input Differential Termination (16): This sets the input termination. Recommended settings are 500, 200, 100, 50 ohms. At lower termination settings, the harmonic distortion performance may show improvement, but the analog input signal amplitude will be reduced.
    4. Input Full Scale Range (25): At high input frequencies, in order to preserve the linearity of the input buffer, it may be beneficial to reduce the input full-scale range in order to get more harmonic distortion performance. This in turn may negatively affect the SNR of the ADC.

Device Setup - NSR Mode

  1. The default Chip Application Mode for the AD6674-750/AD6674-1000 is NSR with a chip decimation ratio of 2 (the AD6674-500 also defaults to NSR mode but with decimation disabled).

    Figure 14. Default Application Mode - NSR/Decimation by 2

  2. The NSR mode settings are configured in the ADCA and ADCB tabs. The NSR defaults to 21% bandwidth mode with a tuning word of 0. Decimate by 2 is enabled by default also on the AD6674-750 and AD6674-1000 (and cannot be disabled in NSR mode).

    Figure 15. Channel A and Channel B NSR Settings

Obtaining an FFT - NSR Mode

  1. The first item to configure in Visual Analog is the input clock frequency. This is the frequency of the input clock and NOT the decimated sample rate (if using decimation). Click in the ADC Data Capture block to open the settings. In this example, 750MHz is the input clock frequency.

    Figure 16. AD6674-750 FFT Data Capture Settings

  2. In order to obtain an FFT with NSR enabled, Visual Analog must be configured correctly. Click on the settings button on the FFT Analysis block and configure the settings in Visual Analog to match the NSR settings that have been programmed into the AD6674. Under Advanced Calculation, click the Enable box, select AD6674 NSR, and then select the appropriate bandwidth mode and tuning word. Make sure to set the Bandwidth to match the mode. When finished, click the Apply button and then the OK button to apply the settings.

    Figure 17. AD6674-750 FFT Analysis NSR Settings

  3. In this example, with an input clock of 750MHz, the output sample rate is 375MSPS. The default JESD204B lane configuration is 4.2.1 (L.M.F). The required REFCLK frequency is 187.5MHz (refer to step 7 in the section “Configuring the Board”).
  4. Click the Run button in Visual Analog and you should see the capture data similar to the plot below.

    Figure 18. AD6674-750 FFT with NSR Enabled

  5. Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the Fund Power reading in the left panel of the VisualAnalog FFT window.) NSR imposes a ~3dB loss in the signal, but does not impact the dynamic range. A -1.0 dBFS input signal will show as -4.0 dBFS in the FFT in Visual Analog.
  6. To save the FFT plot do the following
    1. Click on the Float Form button in the FFT window

      Figure 19. Floating the FFT window

    2. Click on File right Save Form As button and save it to a location of choice

      Figure 20. Saving the FFT

Device Setup - VDR Mode

  1. The default Chip Application Mode for the AD6674-750/AD6674-1000 is NSR with a chip decimation ratio of 2 (the AD6674-500 also defaults to NSR mode but with decimation disabled). The settings in the ADCBase0 tab must be changed to configure the AD6674 into VDR mode. To set up the AD6674 for VDR mode change the Chip Application Mode in register 0x200 to Variable Dynamic Range (VDR) Mode and set the Chip Decimation Ratio in register 0x201 to Full Sample Rate.

    Figure 21. Set Application Mode to VDR

  2. The VDR mode tuning word can be configured in the ADC A and ADC B tabs. VDR defaults to 25% bandwidth complex mode with a tuning word of 0. The tuning word can be changed using the VDR Tuner Frequency selection (register 0x434). See the AD6674 data sheet for more details on the available bandwidth modes and tuning words.

    Figure 22. Channel A and Channel B VDR Settings

  3. Using the default lane configuration in the AD6674 (L.M.F = 4.2.1) the JESD204B lane rate will be 7.5 Gbps which means the PLL must be set to Maximum Lane Rate Mode (0x56E) int he ADCBase3 tab in SPIController.

    Figure 23. PLL Encode Settings

Obtaining an FFT - VDR Mode

  1. The first item to configure in Visual Analog is the input clock frequency. This is the frequency of the input clock and NOT the decimated sample rate (if using decimation). Click in the ADC Data Capture block to open the settings. In this example, 750MHz is the input clock frequency.

    Figure 24. AD6674-750 FFT Data Capture Settings

    1. In this example, with an input clock of 750MHz, the output sample rate is 750MSPS. The default JESD204B lane configuration is 4.2.1 (L.M.F). The required REFCLK frequency is 375MHz (refer to step 7 in the section “Configuring the Board”).
  2. Click the Run button in Visual Analog and you should see the capture data similar to the plot below.

    Figure 25. AD6674-750 FFT with VDR Enabled

  3. Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the Fund Power reading in the left panel of the VisualAnalog FFT window.) VDR imposes no loss on the input signal so a -1.0 dBFS input signal will show as -1.0 dBFS in the FFT in Visual Analog.
  4. To save the FFT plot do the following
    1. Click on the Float Form button in the FFT window

      Figure 26. Floating the FFT window

    2. Click on File right Save Form As button and save it to a location of choice

      Figure 27. Saving the FFT

Setting up SPIController to Use Control Bits as VDR Punish Bits and the VDR High/Low Resolution Bit - VDR Mode

  1. The first step go to the ADCBase2 tab in SPIController to set up the control bits to select the VDR indicator bits. In this example Control Bit 2 is set to VDR Punish Bit 1, Control Bit 1 is set to VDR Punish Bit 0, and Control Bit 0 is set to the VDR High/Low resolution bit. (Similarly, the control bits may be set up to function as Overrange, Signal Monitor (SMON), or Fast Detect (FD) indicators.)

    Figure 28. SPIController ADCBase2 Settings for VDR Indicators in the Control Bits

  2. Next go to the ADCBase4 tab to set up the control bits to select the VDR indicator bits. In this example three control bits are sent per sample. In order to accommodate three control bits, the converter resolution (N) must be set to 13 bits (there are 16 available bits in the JESD204B data word and if three are used for control bits there are 13 bits available for the converter sample - in this example this means there will only be 13 bits available instead of the 14 bits of converter resolution.

    Figure 29. SPIController ADCBase4 Settings for Enabling the Control Bits

Viewing the VDR Punish Bits and the VDR High/Low Resolution Bit - VDR Mode

  1. The first step is to open a new Logic canvas in VisualAnalog. In the Logic canvas configure the Input Formatter to set the Resolution to 16 bits and the Alignment to 18 bits. This will create the space such that all three control bits can be visible in the Logic canvas.

    Figure 30. Input Formatter Settings for VDR Indicators in the Control Bits

  2. Next configure the Logic Analysis block for the data alignement. Set the High Bit to 15 and the low bit to 0. This will align the canvas such that all three control bits can be visible in the Logic canvas.

    Figure 31. Logic Analysis Settings for Bit Alignment

  3. These settings will create the space in the Logic Canvas display so that all three control bits available in the JESD204B data stream will be visible. (While the example here is for VDR the control bits may be set up to function as Overrange, Signal Monitor (SMON), or Fast Detect (FD) indicators and can be viewed in the output data in a similar manner.)

    Figure 32. Logic Canvas Display Showing Available Control Bits

  4. Once a signal is input that will trigger VDR to operate the VDR punish bits [1:0] and the VDR High/Low resolution bit can be seen in the Logic Canvas display. In this case control bit 2 is VDR punish bit 1, control bit 1 is VDR punish bit 0, and control bit 0 is the VDR High/Low resolution bit.

    Figure 33. Logic Canvas Display Showing Control Bits [2:0] Indicating VDR Status

  5. Note that the data alignment from the FPGA to VisualAnalog will fill in the control bits starting from the LSB location in the Logic Canvas display. In this example data bit two is control bit 2, data bit 1 is control bit 1, and data bit 0 is control bit 0. If only using control bit 2 then this would reside in the data bit 0 location in the Logic Canvas display.

    Figure 34. Logic Canvas Display Showing Control Bit 2 Only

Device Setup - 2 ADCs, 2DDCs, Real Mode Decimate by 2

  1. The default Chip Application Mode for the AD6674-750/AD6674-1000 is NSR with a chip decimation ratio of 2 (the AD6674-500 also defaults to NSR mode but with decimation disabled). The settings in the ADCBase0 tab must be changed to configure the AD6674 to use the DDCs. In this example the AD6674 is set up to use two DDCs (one per ADC channel) with real outputs and a decimation ratio of two. Set the Chip Application Mode in register 0x200 to Two Digital Down Converters and select the Only Real (I) Selected checkbox. Set the Chip Decimation Ratio in register 0x201 to Decimate by 2 Ratio.

    Figure 35. Set Application Mode to 2 DDCs Real Mode Decimate by 2

  2. The DDC settings must be configured in ADCBase1, but first, the tuning step, translation frequency, and DDC Phase Increment must be calculated.
    1. The tuning step is equal to the output sample rate divided by 4096.
      1. tuning step = 375MSPS/4096 = 91552.734375
    2. The translation frequency is equal to the output sample rate divided by 4*(decimation ratio).
      1. translation frequency = 375MSPS/(4*2) = 46875000
    3. The DDC Phase Increment is equal to the translation frequency divided by the tuning step.
      1. DDC Phase Increment = 46875000/91552.734375 = 512
  3. Under DDCO CTRL and DDC1 CTRL in the ADCBase1 tab configure the DDCs to select 6dB Gain, Variable IF Mode, Real(I) Decimate by 2 Filter Selection, Both Input Sample Selections to Channel A for DDC0 and Channel B for DDC1, and the DDC Phase Increment to the calculated value of 512
    1. After changing DDC selections, perform a soft reset of the DDCs by checking and unchecking the box for DDC Soft Reset under the DDC Synchronization CTRL Reg (300).

      Figure 36. Channel A and Channel B DDC Settings

  4. Using the default lane configuration in the AD6674 (L.M.F = 4.2.1) the JESD204B lane rate will be 3.75Gbps which means that the PLL needs to be set to Low Lane Rate Mode (0x56E) in the ADCBase3 tab in SPIController. This is the default setting so no change is needed.

Obtaining an FFT - 2 ADCs, 2DDCs, Real Mode Decimate by 2

  1. 1. The first item to configure in Visual Analog is the input clock frequency. This is the frequency of the input clock and NOT the decimated sample rate (if using decimation). Click in the ADC Data Capture block to open the settings. In this example, 750MHz is the input clock frequency. In addition, the DDC data must be selected under the Output Data section. DDC0 and DDC1 are being used in the AD6674 so this must be selected under the ADC Data Capture Settings.

    Figure 37. AD6674-750 FFT Data Capture Settings

    1. In this example, with an input clock of 750MHz, the output sample rate is 375MSPS. The default JESD204B lane configuration is 4.2.1 (L.M.F). The required REFCLK frequency is 187.5MHz (refer to step 7 in the section “Configuring the Board”).
  2. Click the Run button in Visual Analog and you should see the capture data similar to the plot below.

    Figure 38. AD6674-750 FFT with 2 DDCs in Real Mode with Dec2 Enabled

  3. Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the Fund Power reading in the left panel of the VisualAnalog FFT window.) Real DDC operation imposes ~0.7 dB loss on the input signal but does not impact the dynamic range. A -1.0 dBFS input signal will show as -1.7 dBFS in the FFT in Visual Analog.
  4. To save the FFT plot do the following
    1. Click on the Float Form button in the FFT window

      Figure 39. Floating the FFT window

    2. Click on File right Save Form As button and save it to a location of choice

      Figure 40. Saving the FFT

Device Setup - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2

  1. The default Chip Application Mode for the AD6674 is Noise Shaped Requantizer (NSR) Mode with the Chip Decimation Ratio of 2 (decimation is disabled on the AD6674-500). The settings in the ADCBase0 tab must be changed to configure the AD6674 to use the DDC. In this example the AD6674 will be set up to use one DDCs with a complex ZIF output (NCO bypassed) and a decimation ration of two. Set the Chip Application Mode in register 0x200 to One Digital Down Converter and make sure the Only Real (I) Selected checkbox is NOT checked. Set the Chip Decimation Ratio in register 0x201 to Decimate by 2 Ratio.

    Figure 41. Set Application Mode to 1 DDC Complex ZIF Mode Decimate by 2

  2. The DDC settings must be configured under DDCO CTRL in the ADCBase1 tab configure the DDC to select Complex Mixer Selection, 0 Hz IF Mode, Decimate by 2 Filter Selection, Real (I) Input Sample Selection to Channel A for DDC0, and Complex (Q) Input Sample Selection to Channel B.
    1. After changing DDC selections, perform a soft reset of the DDCs by checking and unchecking the box for DDC Soft Reset under the DDC Synchronization CTRL Reg (300).

      Figure 42. DDC Settings for Complex ZIF Mode

  3. Using the default lane configuration in the AD6674 (L.M.F = 4.2.1) the JESD204B lane rate will be 3.75Gbps which means that the PLL needs to be set to Low Lane Rate Mode (0x56E) in the ADCBase3 tab in SPIController. This is the default setting so no change is needed.

Obtaining an FFT - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2

  1. The first item to configure in Visual Analog is the input clock frequency. This is the frequency of the input clock and NOT the decimated sample rate (if using decimation). Click in the ADC Data Capture block to open the settings. In this example, 750MHz is the input clock frequency. In addition, the DDC data must be selected under the Output Data section. DDC0 is being used in the AD6674 so this must be selected under the ADC Data Capture Settings.

    Figure 43. AD6674-750 FFT Data Capture Settings

    1. In this example, with an input clock of 750MHz, the output sample rate is 750MSPS. The default JESD204B lane configuration is 4.2.1 (L.M.F). The output sample rate is 375MSPS and the required REFCLK frequency is 187.5MHz (refer to step 7 in the section “Configuring the Board”).
  2. In order to exclude the image frequency from the SFDR measurements, configure Visual Analog to remove the image from its calculations. This is done under the FFT Analysis settings. Under the User-Defined tab add a new row by clicking Add. Name it ‘Image’. Use a symbol such as the # and set the Freq to ‘-fund’. Set the Single-Side Band to 3 Bins and set it as ‘Spur, Exclude’. Once done, select the row, and then hit the Move Up button to place this new row just below the row with Fund.

    Figure 44. AD6674-750 FFT Analysis Settings for Complex Image

  3. Click the Run button in Visual Analog and you should see the capture data similar to the plot below.

    Figure 45. AD6674-750 FFT with 1 DDC in Complex ZIF Mode with Dec2 Enabled

  4. Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the “Fund Power” reading in the left panel of the VisualAnalog FFT window.) Complex DDC operation imposes ~1dB loss in the signal, but does not impact the dynamic range. A -1dBFS input signal will show as -2dBFS in Visual Analog.
  5. To save the FFT plot do the following
    1. Click on the Float Form button in the FFT window

      Figure 46. Floating the FFT window

    2. Click on File right Save Form As button and save it to a location of choice

      Figure 47. Saving the FFT

Troubleshooting Tips

FFT plot appears abnormal

  • If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure you are not overdriving the ADC. Reduce input level if necessary.
  • In VisualAnalog, Click on the Settings button in the Input Formatter block. Check that Number Format is set to the correct encoding (twos compliment by default). Repeat for the other channel.
  • Issue a Data Path Soft Reset through SPIController Global tab as shown in Figure 46

    Figure 48. Issuing a data path soft reset through SPIController

The FFT plot appears normal, but performance is poor.

  • Make sure you are using the appropriate band-pass filter on the analog input.
  • Make sure the signal generators for the clock and the analog input are clean (low phase noise).
  • If you are using non-coherent sampling, change the analog input frequency slightly, or use coherent frequencies.
  • Make sure the SPI config file matches the product being evaluated.

The FFT window remains blank after the Run button is clicked

  • Make sure the evaluation board is securely connected to the ADS7-V1.
  • Make sure the FPGA has been programmed by verifying that the Config DONE LED is illuminated on the ADS7-V1. If this LED is not illuminated reprogram the FPGA through VisualAnalog. If the LED still does not illuminate disconnect the USB and power cord for 15 seconds. Connect again and repeat the ADS7-V1 setup process.
  • Make sure the correct FPGA bin file was used to program the FPGA.
  • Be sure that the correct sample rate is programmed. Click on the Settings button in the ADC Data Capture block in VisualAnalog, and verify that the Clock Frequency is properly set.

    Figure 49. Setting the correct clock frequeency in VisualAnalog

  • Ensure that the REFCLOCK is ON and set to the appropriate frequency.
  • Restart SPIController.

VisualAnalog indicates that the “FIFO capture timed out” or “FIFO not ready for read back”

  • Make sure all power and USB connections are secure.
  • Make sure that the REFCLOCK is ON and set to the appropriate frequency.

VisualAnalog displays a blank FFT when the RUN button is clicked

  • Ensure that the clock to the ADC is supplied. Using SPIController ADCBase0 tab the status of the clock can be read out.

    Figure 50. Clock Detection Status Register

  • Ensure that the ADC's PLL is locked by checking the status of the PLL lock detect register 0x56F. This can be done using SPIController.
resources/eval/ad6674-1000ebz.txt · Last modified: 19 Aug 2015 17:38 by J.Harris