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====== Basic internals of Pluto ======

The basic block diagram of the ADALM-PLUTO is pretty easy to understand. It has two antennas, where the analog Radio Frequency energy goes in/out, and a single USB connector, where digital data also goes in/out to a host system. However, there is more going on that just RF to bits.

Radio Frequency to bits is difficult task that many have solved [[wp>History_of_radio|over the years]]. Starting as a pure analog problem (and solution), people have been working on this for a long time, and it's always interesting to better understand how long people have been working on these types of problems.
  * [[wp>James_Clerk_Maxwell|James Clerk Maxwell]] published //[[wp>A_Treatise_on_Electricity_and_Magnetism|A Treatise on Electricity and Magnetism]]// in 1873
  * [[wp>Heinrich_Hertz|Heinrich Rudolf Hertz]] was transmitting and receiving EM waves, and published papers on them  in 1887 and 1890. ((surprisingly Hertz considered these results as being of little practical value)).
  * [[wp>Guglielmo_Marconi|Guglielmo Marconi]] developed the first apparatus for long distance radio communication, during the summer of 1895, transmitting signals up to 2 miles (3.2 km) and over hills.
  * [[wp>Reginald_Fessenden|Reginald A. Fessenden]] became the first person to send audio (wireless telephony) by means of electromagnetic waves, transmitting over a distance of about 1.6 kilometers in December 1900, and six years later on Christmas Eve 1906 he became the first person to make a public radio broadcast.
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  * [[wp>Edwin_Howard_Armstrong|Edwin Armstrong]] developed the [[wp>Superheterodyne_receiver|supersonic heterodyne]] receiver as part of his work during WW I in 1918; and Wide-band [[wp>Frequency_modulation|frequency modulation]] between 1928 and 1933.
  *  British researchers, trying to solve some superhet issues, developed the [[wp>Direct-conversion_receiver|homodyne]] in 1932. The design was later renamed the synchrodyne, and is now sometimes refered to as direct conversion or zero-IF.

For nearly the last hundred years, radio design and architecture hasn't changed that much. While many designers and engineers have made vast improvements in devices (from tubes to transistors to integrated circuits), and implementations (shielding, noise reduction, etc), the fundamental architecture that radio engineers work with is historic((according to the [[https://www.nps.gov/nr/faq.htm#howold|National Register of Historic Places]] a building should be fifty years old to be //historic//, so I think this is an acceptable adjective for technological invention)). 

The radio inside the ADALM-PLUTO is the [[/resources/eval/user-guides/ad-fmcomms2-ebz/ad9361|AD9363]], is a high performance, highly integrated RF agile transceiver, based on is a direct conversion receivers. 
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  * The receive subsystem includes a low noise amplifier (LNA), the direct conversion mixer, configurable analog filters, a high speed analog to digital converter (ADC), digital decimation filters, and a 128-tap finite impulse response (FIR) filters to produce a 12-bit output signal at the appropriate sample rate. The receive chain is augmented with configurable automatic gain control (AGC) or manual gain modes, dc offset correction, quadrature correction. The resulting received I and Q signals are passed onto the to the digital baseband processor, in this case the Xilinx Zynq SoC.
  * The transmit subsystem also use a direct conversion architecture. Accepting 12-bit I and Q samples from the baseband processor (in this case, the same Xilinx Zynq SoC), running them through the 128-tap finite impulse response (FIR) filters, digital interpolation filters, a high speed digital to analog converter (DAC), an analog filter, the direct conversion mixers, and small power amplifier (PA) out to the antenna.
  * Fully integrated phase-locked loops (PLLs) inside the AD9363 provide clocks and local oscillators for receive and transmit channels, and clocks for the ADC, DAC and output sample rate.

The Xilinx Zynq All Programmable SoC (AP SoC) integrates the software programmability of an ARM-based processor with the hardware programmability of an FPGA, enabling hardware acceleration while integrating CPU, DSP, ASSP, and mixed signal functionality on a single device. The devices feature a single-core ARM Cortex™-A9 processor mated with 28nm Artix®-7 based programmable logic. Outfitted with commonly used hardened peripherals (USB, SPI, etc),
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