This version (04 Jul 2019 18:01) was approved by Robin Getz.
Table of Contents
Controlling GPIOs on the ADALM-PLUTO
Available GPIOs
Source is the schematic.
Programmable Logic (PL)
| Zynq 7010 Pin | Zynq Pin Name | Schematic Net | PCB Test Point |
|---|---|---|---|
| K13 | IO_L10N_T1_34 | PL_GPIO0 | L10P |
| M12 | IO_L12N_T1_MRCC_34 | PL_GPIO1 | L12N |
| R10 | IO_L24N_T3_34 | PL_GPIO2 | L24N |
Processor System (PS)
| Zynq 7010 Pin | Zynq Pin Name | Schematic Net | PCB Test Point |
|---|---|---|---|
| D8 | PS_MIO0_500 | PS_GPIO0 | MIO0 |
| B10 | PS_MIO11_500 | PS_GPIO1 | MIO10 |
| D6 | PS_MIO10_500 | PS_GPIO2 | MIO11 |
| B5 | PS_MIO9_500 | PS_GPIO3 | MIO09 |
| C13 | PS_MIO53_501 | PS_GPIO4 | MIO53 |
| D13 | PS_MIO49_501 | PS_GPIO5 | MIO49 |
| B12 | PS_MIO48_501 | PS_GPIO6 | MIO48 |
Location
Controlling the GPIOs
university/tools/pluto/devs/controlling_gpios.txt · Last modified: 04 Jul 2019 18:01 by Robin Getz