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university:labs:closed_loop_buck_adalm2000 [10 Mar 2020 20:40] – Add first closed-loop vmode experiment Mark Thorenuniversity:labs:closed_loop_buck_adalm2000 [04 Nov 2021 16:44] (current) – [Activity 4: Current-mode loop optimization] add links to power labs, university home Mark Thoren
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 Several analysis methods will be demonstrated using LTspice - AC simulation of continuous time circuits, extracting the frequency response of switching circuits using step and measure techniques in LTspice, Middlebrook's method for extracting open loop gain from a closed loop system. Where possible, these will be replicated on the ADALM-SR1 hardware. Several analysis methods will be demonstrated using LTspice - AC simulation of continuous time circuits, extracting the frequency response of switching circuits using step and measure techniques in LTspice, Middlebrook's method for extracting open loop gain from a closed loop system. Where possible, these will be replicated on the ADALM-SR1 hardware.
  
-==== Materials ====+===== Materials =====
   * ADALM2000 (M2K) Active Learning module OR:   * ADALM2000 (M2K) Active Learning module OR:
     * Two-channel oscilloscope with external trigger input     * Two-channel oscilloscope with external trigger input
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   * ADALM-SR1 Switching Regulator Active Learning Module   * ADALM-SR1 Switching Regulator Active Learning Module
     * User Guide: [[university:tools:lab_hw:adalm-sr1|ADALM-SR1 hardware]]     * User Guide: [[university:tools:lab_hw:adalm-sr1|ADALM-SR1 hardware]]
-  * CN0508-RPIZ power supply OR:+  * [[resources:eval:user-guides:circuits-from-the-lab:cn0508|EVAL-CN0508-RPIZ]] power supply OR:
     * 0-12V, 3A Adjustable benchtop power supply     * 0-12V, 3A Adjustable benchtop power supply
 +  * LTspice files for this exercise
 +    * [[downgit>education_tools/tree/sr1/m2k/ltspice/cl_buck|LTspice files for this exercise]]
 +
 ===== Background ===== ===== Background =====
-Applying traditional control theory to switching regulators presents some challenges. A continuous time system - even a "messy" one that may be nonlinear or time-variant - can often be approximated by a linear system by limiting the range of amplitudes and / or frequencies. There is no such good fortune with switching regulators - the power stage inherently involves a switching circuit that traverses several distinct states. One approach to this problem is to derive a continuous time model that approximates the behavior of the power stage at the timescales of interest. Once this model is derived, traditional methods can be used to design feedback compensators to meet the application requirements. [[https://www.analog.com/media/en/technical-documentation/application-notes/AN149fa.pdf|Application Note 149: Modeling and Loop Compensation Design of+Applying traditional control theory to switching regulators presents some challenges. A continuous time system - even a "messy" one that may be nonlinear or time-variant - can often be approximated by a linear system by limiting the range of amplitudes and / or frequencies. There is no such good fortune with switching regulators - the power stage inherently involves a switching circuit that traverses several distinct states. One approach to this problem is to derive a continuous time model that approximates the behavior of the power stage at the timescales of interest. Once this model is derived, traditional methods can be used to design feedback compensators to meet the application requirements. [[adi>media/en/technical-documentation/application-notes/AN149fa.pdf|Application Note 149: Modeling and Loop Compensation Design of
 Switching Mode Power Supplies]] is an excellent resource for this general approach, while this lab exercise will focus on the specific case of the ADALM-SR1. Some additional resources on the subject are:\\ Switching Mode Power Supplies]] is an excellent resource for this general approach, while this lab exercise will focus on the specific case of the ADALM-SR1. Some additional resources on the subject are:\\
-[[https://www.analog.com/en/technical-articles/loop-gain-and-its-effect-on-analog-control-systems.html|Loop Gain and its Effect on Analog Control Systems]]\\ +[[adi>en/technical-articles/loop-gain-and-its-effect-on-analog-control-systems.html|Loop Gain and its Effect on Analog Control Systems]]\\ 
-[[https://www.analog.com/media/en/technical-documentation/application-notes/an170f.pdf| Application Note 170: Honing the Adjustable Compensation Feature of Power System Management Controllers]]\\ +[[adi>media/en/technical-documentation/application-notes/an170f.pdf| Application Note 170: Honing the Adjustable Compensation Feature of Power System Management Controllers]]\\ 
-[[https://www.analog.com/media/en/technical-documentation/application-notes/AN140fb.pdf|Application Note 140 Basic Concepts of Linear Regulator and Switching Mode Power Supplies]]\\+[[adi>media/en/technical-documentation/application-notes/AN140fb.pdf|Application Note 140 Basic Concepts of Linear Regulator and Switching Mode Power Supplies]]\\
  
 ===== Activity 1: An Overcompensated Voltage-Mode Buck Converter ===== ===== Activity 1: An Overcompensated Voltage-Mode Buck Converter =====
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 This is called "current mode" control because of the error signal (how far we are off from the desired output voltage) is directly compared to the peak inductor controlling the current in the circuit. Conceptually this makes the inductor a controlled current source.   This is called "current mode" control because of the error signal (how far we are off from the desired output voltage) is directly compared to the peak inductor controlling the current in the circuit. Conceptually this makes the inductor a controlled current source.  
 +
 +<WRAP todo>
 +Consider Reordering, put after Voltage Mode is done.
 +</WRAP>
  
 ===== Activity 3: Voltage-mode loop optimization ===== ===== Activity 3: Voltage-mode loop optimization =====
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 ==== Buck Power Stage Continuous model, voltage-mode ==== ==== Buck Power Stage Continuous model, voltage-mode ====
-Consider the ADALM-SR1 power stage when configured for open-loop, duty cycle control mode:+Consider the ADALM-SR1 power stage when configured for open-loop, duty cycle control mode, with the LTC6992-3 PWM generator providing the gate control:\\
  
-(Figure)+{{ :university:labs:closed_loop_buck_adalm2000:CL_Buck_vmode_powers_stage_sw.png?direct&800 |}} 
 +<WRAP centeralign> Figure 5. Buck Switching Power Stage </WRAP>\\
  
-And the LTC6992 PWM generator:+The property of this circuit that needs to be extracted is the transfer function from a "wiggle" at the MOD pin to a "wiggle" at the output (labeled "a"). Intuitively, sweeping the voltage at the MOD pin from 0V to 1.0V will produce a 0 to 100% duty cycle at its OUT pin. The power stage will then translate this duty cycle to an output voltage of 0V to 12V, on the condition that the circuit is operating in CCM. Following the logic in AN149, this circuit SHOULD be roughly equivalent to the following, purely linear circuit:
  
-(Figure)+{{ :university:labs:closed_loop_buck_adalm2000:CL_Buck_vmode_powers_stage_lin.png?direct&800 |}} 
 +<WRAP centeralign> Figure 6. Buck Linearized Power Stage </WRAP>\\
  
 +noting that the inductance, output capacitors, and load resistor are identical to the switched circuit. E1 is a voltage-controlled voltage source, representing the inherent gain of 12 in the switching circuit. This circuit may look familiar - it is an RLC lowpass filter, so we should be able to simulate it as such with a .AC analysis. Including this SPICE directive:
  
-The property of this circuit that needs to be extracted is the transfer function from a "wiggle" at the MOD pin to a "wiggle" at the output (labeled "a"). Intuitively, sweeping the voltage at the MOD pin from 0V to 1.0V will produce a 0 to 100% duty cycle at its OUT pin. The power stage will then translate this duty cycle to an output voltage of 0V to 10V, on the condition that the circuit is operating in CCM. Following the logic in AN149, this circuit SHOULD be roughly equivalent to the following, purely linear circuit: +<code> 
- +.ac dec 25 5 50k 
-(Figure) +</code> 
- +will allow us to measure the transfer function from 5Hz to 50kHz, with the result shown here:
- +
-noting that the inductance, output capacitors, and load resistor are identical. E1 represents the inherent gain of 10 in the switching circuit. This circuit may look familiar - it is an RLC lowpass filter, so we should be able to simulate it as such with a .AC analysis. Including this SPICE directive: +
- +
-.ac dec 25 100 100k +
- +
-will allow us to measure the transfer function from 100Hz to 100kHz, with the result shown here:+
  
-(Figure)+{{ :university:labs:closed_loop_buck_adalm2000:CL_Buck_vmode_powers_stage_lin_response_ac.png?direct&600 |}} 
 +<WRAP centeralign> Figure 7. Buck Linearized Power Stage Response, AC Analysis </WRAP>\\
  
 Which is great! But... remember that we can't use a .AC directive on the switching circuit because it has no operating point around which it can be analyzed. What we can do is apply a stepped frequency / measure analysis, described in the link below. Replacing the .AC directive with the following: Which is great! But... remember that we can't use a .AC directive on the switching circuit because it has no operating point around which it can be analyzed. What we can do is apply a stepped frequency / measure analysis, described in the link below. Replacing the .AC directive with the following:
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 .param t0=0.01m .param t0=0.01m
 .tran 0 {t0+25/freq} {t0} .tran 0 {t0+25/freq} {t0}
-.step dec param freq 100 100K 10+.step dec param freq 5 50K 5
 .save V(a) V(b) .save V(a) V(b)
 .option plotwinsize=0 numdgt=15 .option plotwinsize=0 numdgt=15
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 performs a roughly equivalent analysis, stepping the input frequency from 100Hz to 100kHz, but at each step, capturing the input and output waveforms and performing a Fourier analysis to extract gain and phase. The result is shown below: performs a roughly equivalent analysis, stepping the input frequency from 100Hz to 100kHz, but at each step, capturing the input and output waveforms and performing a Fourier analysis to extract gain and phase. The result is shown below:
  
-(Figure)+{{ :university:labs:closed_loop_buck_adalm2000:CL_Buck_vmode_powers_stage_lin_response_step.png?direct&600 |}} 
 +<WRAP centeralign> Figure 8. Buck Linearized Power Stage Response, Stepped Analysis </WRAP>\\
  
 So now that we're convinced that these two simulation methods produce approximately the same result (Note: dig into discrepancies that do exist!), we can apply the second method to the switching circuit, with the following result: So now that we're convinced that these two simulation methods produce approximately the same result (Note: dig into discrepancies that do exist!), we can apply the second method to the switching circuit, with the following result:
  
-(Figure)+{{ :university:labs:closed_loop_buck_adalm2000:CL_Buck_vmode_powers_stage_sw_response.png?direct&600 |}} 
 +<WRAP centeralign> Figure 9. Buck Switching Power Stage Response </WRAP>\\
  
-At low frequencies, it is remarkably similar! Note the strange behavior around 10kHz - this is because the power stage is switching at 100kHz <<pay attention if we change this>>, so it only has 20k discrete "opportunities" to modify the output voltage per second, and thus can be looked at as a sampled system - and all sampled systems are subject to Nyquist criterion, and will alias if this is violated. (We can dig into that later...)+At low frequencies, it is remarkably similar! Note the strange behavior around 10kHz - this is because the power stage is switching at 20kHz, so it only has 20,000 discrete "opportunities" to modify the output voltage per second, and thus can be looked at as a sampled system - and all sampled systems are subject to Nyquist criterion, and will alias if this is violated. (We can dig into that later...)
  
-Let's take our newfound knowledge of the power stage, and wrap the overcompensated compensator around it.+But we found the dominant pole of the power stage - about 362Hz for the linearized model, and about 232Hz for the switching model! 
 +<WRAP todo> 
 +Dig into discrepency - are we discontinuous? 
 +</WRAP> 
 + 
 +The last step, naturally is to measure the actual power stage and see how it compares to simulation. Configure the ADALM-SR1 as shown in Figure 10 below. 
 + 
 +{{ :university:labs:closed_loop_buck_adalm2000:SR1_config_CL_Vmode_buck_pwr_stage_char.png?direct&1000 |}} 
 +<WRAP centeralign> Figure 10. ADALM-SR1 Config. for Voltage Mode Buck Power Stage Response  </WRAP> 
 + 
 +This is also the point in our experiment where things get "interesting", in the sense that real-world messiness (switching noise) needs to be carefully balanced with signal levels and measurement resolution: No matter how big you make the inductance and output capacitor, there will always be some switching residue that will obscure the signal you're trying to measure.\\ 
 +  * Applying a large stimulus to the power stage will result in a larger signal that will be easier to measure, however, the response may become nonlinear (distort). 
 +  * Applying a small signal will tend to keep the response more linear, but the smaller output signal will be more difficult to disginguish from noise. 
 + 
 +Start by connecting the ADALM-SR1's auxilary power. Set the input voltage to 12V. In Scopy's Logic Analyzer, verify that the switching frequency is still set to 20kHz. Set the duty cycle such that the output voltage is 5V. At this point the switching circuit is in the same conditions it would be if the loop were still closed, that is, the error integrater would adjust the duty cycle to the same value as we just did. The difference is, IF something did change: if the load were increased or the input voltage dropped, output would drop momentarily, but the error integrator would bring the output back into regulation by increasing the duty cycle. (The opposite would happen if the load were decreased or the input voltage increased - the error integrator would reduce the duty cycle.) 
 + 
 +To determine the frequency response of the power stage around this operating point, we need to sinusoidally stimulate ("wiggle") the duty cycle around, and see how the output responds. Intuitively, if you wiggle the MOD pin slowly, the delay through the LTC6992-3 will be negligible, and the delay due to the L-C filtering effect of the inductor and output capacitors will also be negligible. But as you continue to increas the frequency of the stimulus, there will be a measurable phase lag at the output, and the amplitude of the output "wiggle" will be smaller than it was at lower frequencies. 
 + 
 +Ideally, we would do a complete frequency response and try to replicate the full Bode plot from the LTspice simulation, and Scopy does have a network analyzer feature that would do this very nicely for the linearized circuit. However, the noise that is present on our measured signal has the potential to confuse the network analyzer. But we can make some simplifying assumptions and measure the -3dB frequency (where the amplitude drops to 0.707 of the original amplitude), as well as the phase lag at that frequency. 
 + 
 +Set the Signal Generator Channel 1 (W1 in Figure 10) to 25Hz sinewave, 500mV p-p amplitude. This signal is attenuated by the onboard protection circuitry, and the resulting signal at the LTC6992-3 MOD pin is measured at P23 with scope channel 1. (Pilot revision boards will need to use a jumper with extended pins to accommodate the scope input.) Scope Channel 2 measures the output voltage, which it is AC coupled (P9 NOT installed.) AC coupling is used because we're only interested in the "wiggle" around the 5V steady-state operating point, and the 5V DC component of the signal would force the scope into the 20V range, greatly reducing its ability to resolve small signals.  
 + 
 +Set the oscilloscope to 10ms/div, CH1 to 5mV/div, and CH2 to 50mV/div. We know that a duty cyle range of 0 to 100% should correspond to an output voltage of 0 to 12V, which is "a bit more than 10", so the CH2 amplitude should apper about 20% larger than the CH1 amplitude. But let's illuminate one more subtelety about our test equipment - the output trace looks suspiciously "clean" given the regulator's switching nature, doesn't it? And the stimulus trace has some strange "steppiness" as well. It turns out that there are several filters in the ADALM2000 itself and Scopy, and we can use them to our advantage. 
 + 
 +{{ :university:labs:closed_loop_buck_adalm2000:CL_Buck_vmode_powers_stage_actual_filtered.png?direct&600 |}} 
 +<WRAP centeralign> Figure 11. Buck Switching Power Stage, 25Hz, Filters Enabled </WRAP>\\ 
 + 
 +Open the Settings (gear icon) in Scopy, and de-select sample rate filtering. The switching noise becomes MUCH more visible! Because the switching noise frequency is much higher than our signal of interest, as is the cutoff frequency of the sample rate filter, the impact of the filter on the measurement is negligible. The main reason for checking out the unfiltered mode is to get a feel for what is "really there", and how to process this data to make it more useful. Re-enable the filter. 
 + 
 +{{ :university:labs:closed_loop_buck_adalm2000:CL_Buck_vmode_powers_stage_actual_noisy.png?direct&600 |}} 
 +<WRAP centeralign> Figure 12. Buck Switching Power Stage, 25Hz, Scope Unfiltered </WRAP>\\ 
 + 
 +<WRAP tip> 
 +If you are using a benchtop scope, the filtering options may be different. One method of reducing noise that works well is to use "Acquisition Mode" - Set the scope to acquire and average some number of traces (start with 16), and trigger on the waveform generator. 
 +</WRAP> 
 + 
 +The next step is to measure the relative amplitude of both the stimulus and the output, as well as the delay, or phase difference, between the two. Scopy can measure and display these, however it's always a good idea to double-check by using cursors. Note the ratio of output wiggle to input wiggle (136mV / 10mV = 13.6 for Figure 11.) 
 + 
 +Next, increase the frequency in 10Hz increments, until the output amplitude drops to 70.7% of its initial value. (about 160Hz in Figure 13) This is the -3dB, or cutoff frequency of the power stage. You should also see a delay between the stimulus and output - use the time cursors to measure the time between the peak of the stimulus waveform and the peak of the output waveform. 
 + 
 +{{ :university:labs:closed_loop_buck_adalm2000:CL_Buck_vmode_powers_stage_at_cutoff.png?direct&600 |}} 
 +<WRAP centeralign> Figure 13. Buck Switching Power Stage, -3dB at 160 Hz </WRAP>\\ 
 + 
 +Calculate the phase with the following formula: 
 + 
 +phase = 360 * delay * Frequency 
 + 
 +or about 360 * 990μs * 160Hz = 57 degrees. 
 + 
 +Let's take our newfound knowledge of the power stage, and analyze the closed-loop response with the overcompensated compensator.
  
 (predict linearized response, phase margin, then compare with ADALM-SR1 results) (predict linearized response, phase margin, then compare with ADALM-SR1 results)
  
-(Measured results with ADALM-SR1)+(Measured results with ADALM-SR1 using Middlebrook circuit, step response and cutoff.)
  
 (speed up compensator to some reasonable fraction of power stage, predict result, compare against ADALM-SR1) (speed up compensator to some reasonable fraction of power stage, predict result, compare against ADALM-SR1)
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 Intro on differences in control dynamics... Intro on differences in control dynamics...
  
 +<WRAP todo>
 +
 +</WRAP>
  
 +**Return to [[university:labs:power|Power Based Lab Activity Material]]**\\
 +**Return to [[university:|Engineering University Program Home]]**
university/labs/closed_loop_buck_adalm2000.1583869222.txt.gz · Last modified: 10 Mar 2020 20:40 by Mark Thoren

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