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--- university:courses:electronics:electronics-lab-adc [24 Sep 2019 13:02] – Vin computation steps Pop Andreea
+++ university:courses:electronics:electronics-lab-adc [24 Sep 2019 13:19] – [Procedure] Pop Andreea
@@ Line 80: / Line 80: @@
 ==== Hardware Setup ====
-Build the circuit presented in figure 7 on your solderless breadboard. This is a  circuit for 2-bit Flash ADC with encoded output..
+Build the circuit presented in figure 7 on your solderless breadboard. This is a  circuit for 2-bit Flash ADC with encoded output.
 <WRAP centeralign> {{ :university:courses:electronics:flash_adc-bb.png?900 |}} </WRAP>
@@ Line 88: / Line 88: @@
 ==== Procedure ====
-Supply the circuit to +/-5V from the power supply. Configure AWG1 of the Signal Generator to Rising Ramp Sawtooth with 5V amplitude peak-to-peak, 2.5 offset and 100Hz frequency. Use AWG2 as 5V constant reference voltage for the ADC.
+Supply the circuit to +/-5V from the power supply. Configure AWG1 of the Signal Generator to Rising Ramp Sawtooth with 5V amplitude peak-to-peak, 2.5 V offset and 100Hz frequency. Use AWG2 as 5V constant reference voltage for the ADC.
 Configure the Logic Analyzer so that the digital channels DIO0, DIO1, DIO2 form a channel group decoded for Unary code and channels DIO6 and DIO7 form a channel group decoded for parralel output.

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