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| university:courses:electronics:electronics-lab-6m [27 Oct 2012 18:56] – [Directions:] Doug Mercer | university:courses:electronics:electronics-lab-6m [25 Jun 2020 22:07] (current) – external edit 127.0.0.1 |
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| ====== Activity 6M. NMOS as a Current Mirror ====== | ====== Activity: NMOS as a Current Mirror ====== |
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| ===== Objective: ===== | ===== Objective: ===== |
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| ===== Materials: ===== | ===== Materials: ===== |
| Analog Discovery Lab hardware\\ | ADALM2000 Active Learning Module\\ |
| Solder-less breadboard\\ | Solder-less breadboard\\ |
| Jumper wires\\ | Jumper wires\\ |
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| <WRAP centeralign> Figure 1 NMOS Current mirror test circuit </WRAP> | <WRAP centeralign> Figure 1 NMOS Current mirror test circuit </WRAP> |
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| | {{ :university:courses:electronics:a6m_nf2.png? |}} |
| | <WRAP centeralign> Figure 2 NMOS Current mirror test circuit breadboard connection </WRAP> |
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| ===== Hardware Setup: ===== | ===== Hardware Setup: ===== |
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| In the current mirror configuration, the opamp serves as a virtual ground at the mirror input (gate) node to convert the voltage steps from AWG 2 ( W2 output ) into current steps through the 1K? resistor. The drain voltage is swept using a ramp from AWG 1(output W1) set to 3V peak to peak with the offset to 1.5V. V<sub>DS</sub> of output device M<sub>2</sub> is measured differentially by scope inputs 1+, 1-. The mirror output current is measured by scope inputs 2+. 2- across 1K? resistor, R<sub>2</sub>. | In the current mirror configuration, the opamp serves as a virtual ground at the mirror input (gate) node to convert the voltage steps from AWG 1 ( W1 output ) into current steps through the 1K? resistor. The drain voltage is swept using a ramp from AWG 1(output W1). Load the stairstep.csv file, set amplitude to 3V peak-to-peak with the offset to 1.5V. |
| | V<sub>DS</sub> of output device M<sub>2</sub> is measured differentially by scope inputs 1+, 1-. The mirror output current is measured by scope inputs 2+. 2- across 1K? resistor, R<sub>2</sub>. |
| If you don't want to use the op-amp configuration the following simplified configuration can be used as well. | If you don't want to use the op-amp configuration the following simplified configuration can be used as well. |
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| {{ :university:courses:electronics:a6m_f2.png?500 |}} | {{ :university:courses:electronics:a6m_f2.png?500 |}} |
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| <WRAP centeralign> Figure 2 simplified test configuration </WRAP> | <WRAP centeralign> Figure 3 simplified test configuration </WRAP> |
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| ===== Hardware Setup: ===== | {{ :university:courses:electronics:a6m_nf4.png? |}} |
| | <WRAP centeralign> Figure 4 Simplified test configuration breadboard connection </WRAP> |
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| ===== Procedure: ===== | ===== Procedure: ===== |
| Two identical transistors with the same gate to source voltage will have the same drain current I<sub>D</sub>. The second transistor, M<sub>2</sub>, in effect mirrors the current in the first, M<sub>1</sub>. Remembering the drain current to gate source voltage relationship for a MOS transistor: | Two identical transistors with the same gate to source voltage will have the same drain current I<sub>D</sub>. The second transistor, M<sub>2</sub>, in effect mirrors the current in the first, M<sub>1</sub>. Remembering the drain current to gate source voltage relationship for a MOS transistor: |
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| {{ :university:courses:electronics:a6m_e1.png?250 |}} | {{ :university:courses:electronics:a6m_ne1.png? 250 |}} |
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| where K =μ<sub>n</sub>C<sub>ox</sub>/2<sub></sub> and λ can be taken as process technology constants.\\ | where K =μ<sub>n</sub>C<sub>ox</sub>/2<sub></sub> and λ can be taken as process technology constants.\\ |
| Identical transistors by definition have the same W/L and process technology constants. In the simple current mirror, both transistors have the same V<sub>GS</sub>. Thus, both transistors will have the same I<sub>D</sub>. Since no current flows in the gate terminal of a FET I<sub>in</sub> = I<sub>out</sub>. | Identical transistors by definition have the same W/L and process technology constants. In the simple current mirror, both transistors have the same V<sub>GS</sub>. Thus, both transistors will have the same I<sub>D</sub>. Since no current flows in the gate terminal of a FET I<sub>in</sub> = I<sub>out</sub>. |
| | {{ :university:courses:electronics:a6m_nf5.png?500 |}} |
| | <WRAP centeralign> Figure 5 Current Mirror waveform </WRAP> |
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| | <WRAP round download> |
| | **Resources:** |
| | * Fritzing files: [[downgit>education_tools/tree/master/m2k/fritzing/mos_current_mirror_bb | mos_current_mirror_bb]] |
| | * LTspice files: [[downgit>education_tools/tree/master/m2k/ltspice/nmos_cur_mirror_ltspice | mos_current_mirror_ltspice]] |
| | </WRAP> |
| ===== Questions: ===== | ===== Questions: ===== |
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| You are to measure I<sub>in</sub>, Rout seen into the drain of M<sub>2</sub>, the current mirror gain = I<sub>out</sub>/I<sub>in</sub> and determine the Norton and Thevenin equivalent circuits for this mirror. | You are to measure I<sub>in</sub>, Rout seen into the drain of M<sub>2</sub>, the current mirror gain = I<sub>out</sub>/I<sub>in</sub> and determine the Norton and Thevenin equivalent circuits for this mirror. |
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| | **Return to Lab Activity [[university:courses:electronics:labs|Table of Contents]]** |
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