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Activity 4M. NMOS FET characteristic curves

ID vs. VGS curves

Objective:

The purpose of this activity is to investigate the drain current vs. gate voltage characteristics of an NMOS FET transistor.

Materials:

ADALM2000 Active Learning Module
Solder-less breadboard
Jumper wires
1 - 100Ω resistor
1 - Small signal NMOS transistor (CD4007 or ZVN2110A)

Directions:

The drain current vs. gate voltage characteristics of an NMOS transistor can be measure using the ADALM2000 Lab hardware and the following connections as shown in figure 1. Set up the breadboard with the arbitrary waveform generator output W1 attached to the gate terminal of M1. Connect one end of resistor R1 to both the positive Vp supply and the 2+ scope input. Connect the opposite end of resistor R1 to both the drain of M1 and scope inputs 2- and 1+. The source of M1 is connected to ground.

Figure 1 NMOS ID vs VGS setup

Hardware Setup:

Figure 2 NMOS ID vs VDS breadboard circuit

The arbitrary waveform generator should be configured for a 100 Hz triangle wave with 2.5 volt amplitude and 1.25 volt offset. The differential scope channel 2 (2+/-) measures the current in the resistor (and in the transistor). Scope channel 1 should be connected to display the output of the waveform generator. The current flowing through the transistor is the voltage difference 2+ and 2- divided by the resistor value (100Ω).

Procedure:

Figure 3 NMOS ID vs VDS XY plot

Load the captured data in to Excel and calculate the current. Plot the drain current vs. the gate voltage of the transistor (VGS). No drain current should flow when VGS is less than VTHthe threshold voltage of the transistor. The threshold voltage, VTH, can be both positive, for an enhancement mode, and negative, for a depletion mode device. When VGS is greater than VTH, the gate voltage to drain current relationship is quadratic. Now plot the drain current vs. the square of the gate voltage. The line should be straight as seen in the second plot.

Future activities will rely on matching of the threshold voltage, VTH, of at least two FETs. You should record the VTHfor each device you have available and sort them by their threshold voltages.

Questions:

Add Questions here:

ID vs. VDS curves

Objective:

The purpose of this activity is to investigate the drain current ID vs. drain to source voltage VDS characteristic curves of an NMOS FET transistor.

Materials:

1 - 100Ω resistor
1 - Small signal NMOS transistor (CD4007 or ZVN2110A)

Directions:

Starting with the previous breadboard setup, Remove the Vp supply connection and replace it with W1 taken from the gate terminal. Now place W2 on the gate terminal (in place of W1).

Figure 4 NMOS ID vs VDS setup

Hardware Setup:

Figure 5 NMOS ID vs VDS breadboard circuit

The setup is the same as the previous experiment except now Scope channel 1 is set to display the transistor VDS. The drain voltage is swept using a 3 volt peak to peak ramp with an offset equal to 1.5V from the arbitrary waveform generator. VDS is measured by single ended scope input 1+. The drain current is measured by differential scope input 2+/- across the 100Ω resistor R1.

A stair-step waveform will be needed to drive the gate of the transistor. Using the buffer in the Scopy Signal Generator tool, construct a stair-step waveform with 5 levels on channel 2 (W2). Load the following csv file (extract from archive): stair-step.zip. Set the amplitude to 3V and sampleRate to 100Hz.

Procedure:

Figure 6 NMOS ID vs VDS waveforms

Once the VTH of the device is known from the previous measurement, the starting offset for the stair step waveform used on the gate, from waveform generator 2, can be established. The height of the steps should be set, or adjusted according to the gain (mA/V2) of the transistor being measured. This can also be gotten from the previous ID vs. VGS data.

Questions:

Add questions here:

Lab Resources:

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university/courses/electronics/electronics-lab-4m.txt · Last modified: 13 Nov 2018 15:08 by amiclaus