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| university:courses:electronics:electronics-lab-1st [26 Oct 2018 14:14] – [Additional Background on settling time measurements:] add LTspice files Antoniu Miclaus | university:courses:electronics:electronics-lab-1st [03 Nov 2021 20:26] – [Op Amp Settling Time] Doug Mercer |
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| ====== Op Amp Settling Time ====== | ======Activity:Op Amp Settling Time, For ADALM2000====== |
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| ===== Settling Time Background: ===== | ===== Settling Time Background: ===== |
| 1 OP27 op-amp\\ | 1 OP27 op-amp\\ |
| 1 OP37 op-amp\\ | 1 OP37 op-amp\\ |
| 1 OP97 ( slow settling amplifier not normally supplied with the Analog Parts Kit )\\ | 1 OP97 ( slow settling amplifier )\\ |
| 2 0.1uF Capacitors (used to de-couple the Vp and Vn power supplies)\\ | 2 0.1uF Capacitors (used to de-couple the Vp and Vn power supplies)\\ |
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| ==== Hardware Setup: ==== | ==== Hardware Setup: ==== |
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| Waveform generator 1 should be configured for a 60 KHz square wave 1V amplitude and 0 volt offset. Scope channel 1 is used to monitor the input square wave and should be set to 500 mV/div and used as the trigger source. Scope channel 2 is used to alternately measure the op amp output, V<sub>2</sub>, and the Error signal at the wiper of the potentiometer. Channel 2 should be set to 500 mV/div when observing the output of the amplifier but should be set to a more sensitive scale of 100 mV/div when observing the Error signal. | Waveform generator 1 should be configured for a 60 KHz square wave 1V amplitude peak-to-peak and 0 volt offset. Scope channel 1 is used to monitor the input square wave and should be set to 500 mV/div and used as the trigger source. Scope channel 2 is used to alternately measure the op amp output, V<sub>2</sub>, and the Error signal at the wiper of the potentiometer. Channel 2 should be set to 500 mV/div when observing the output of the amplifier but should be set to a more sensitive scale of 100 mV/div when observing the Error signal. |
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| <WRAP centeralign>{{:university:courses:electronics:opamp_settling_time-bb.png|}}</WRAP> | <WRAP centeralign>{{:university:courses:electronics:opamp_settling_time-bb.png|}}</WRAP> |
| Next replace the OP27 amplifier with a OP37 amplifier from the Parts Kit. Again export the Error waveform showing the settling to both rising and falling input steps for inclusion in your Lab report. Overlay the OP37 settling waveform with the saved reference waveform of the OP27. Compare the settling time and general characteristics of each. You should also again store the Error waveform, scope channel 2, for the OP37 as a reference waveform (R2) for future comparison. | Next replace the OP27 amplifier with a OP37 amplifier from the Parts Kit. Again export the Error waveform showing the settling to both rising and falling input steps for inclusion in your Lab report. Overlay the OP37 settling waveform with the saved reference waveform of the OP27. Compare the settling time and general characteristics of each. You should also again store the Error waveform, scope channel 2, for the OP37 as a reference waveform (R2) for future comparison. |
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| Finally replace the OP37 with the much slower settling OP97 amplifier if you have one available. Again export the Error waveform showing the settling to both rising and falling input steps for inclusion in your Lab report. Overlay the OP97 settling waveform with the saved reference waveforms of the OP27 and OP37. Compare the settling time and general characteristics of each. | Finally replace the OP37 with the much slower settling OP97 amplifier. Again export the Error waveform showing the settling to both rising and falling input steps for inclusion in your Lab report. Overlay the OP97 settling waveform with the saved reference waveforms of the OP27 and OP37. Compare the settling time and general characteristics of each. |
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| {{ :university:courses:electronics:opamp_settling_time-wav.png |}} | {{ :university:courses:electronics:opamp_settling_time-wav.png |}} |
| The circuit in figure 4 works best if low capacitance Schottky diodes are used for D<sub>1</sub>, D<sub>2</sub>, D<sub>3</sub>, and the lead lengths on all the connections are minimized. A short length of 50Ω coax can be used to connect the pulse generator to the circuit, however best results are obtained if the test fixture is connected directly to the output of the generator. The pulse generator is adjusted to output a positive-going pulse at "A" which rises from approximately -1.8 V to +0.5 V in less than 5 nSec (assuming the settling time of the test device is in the order of 20 nSec). Shorter rise times may generate ringing, and longer rise times can degrade the test device settling time; therefore some optimization is required in the actual circuit to get best performance. When the pulse generator output "A" goes above 0 V, D<sub>1</sub> begins to conduct, and D<sub>2</sub>/D<sub>3</sub> are reversed biased. The "0V" region of the signal "B" at the input of the device to be tested is flat "by definition"-neglecting the leakage current and stray capacitance of the D<sub>2</sub>-D<sub>3</sub> series combination. The D<sub>1</sub> diode and its 100O resistor help maintain an approximate 50O termination during the time the pulse at "A" is positive. | The circuit in figure 4 works best if low capacitance Schottky diodes are used for D<sub>1</sub>, D<sub>2</sub>, D<sub>3</sub>, and the lead lengths on all the connections are minimized. A short length of 50Ω coax can be used to connect the pulse generator to the circuit, however best results are obtained if the test fixture is connected directly to the output of the generator. The pulse generator is adjusted to output a positive-going pulse at "A" which rises from approximately -1.8 V to +0.5 V in less than 5 nSec (assuming the settling time of the test device is in the order of 20 nSec). Shorter rise times may generate ringing, and longer rise times can degrade the test device settling time; therefore some optimization is required in the actual circuit to get best performance. When the pulse generator output "A" goes above 0 V, D<sub>1</sub> begins to conduct, and D<sub>2</sub>/D<sub>3</sub> are reversed biased. The "0V" region of the signal "B" at the input of the device to be tested is flat "by definition"-neglecting the leakage current and stray capacitance of the D<sub>2</sub>-D<sub>3</sub> series combination. The D<sub>1</sub> diode and its 100O resistor help maintain an approximate 50O termination during the time the pulse at "A" is positive. |
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| | <WRAP round download> |
| **Lab Resources:** | **Lab Resources:** |
| * Fritzing files: [[ https://minhaskamal.github.io/DownGit/#/home?url=https://github.com/analogdevicesinc/education_tools/tree/master/m2k/fritzing/opamp_settling_time_bb | opamp_settling_time_bb]] | * Fritzing files: [[downgit>education_tools/tree/master/m2k/fritzing/opamp_settling_time_bb | opamp_settling_time_bb]] |
| * LTSpice files: [[ https://minhaskamal.github.io/DownGit/#/home?url=https://github.com/analogdevicesinc/education_tools/tree/master/m2k/ltspice/opamp_settling_time_ltspice | opamp_settling_time_ltspice]] | * LTSpice files: [[downgit>education_tools/tree/master/m2k/ltspice/opamp_settling_time_ltspice | opamp_settling_time_ltspice]] |
| | </WRAP> |
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| ==== For further reading: ==== | ==== For further reading: ==== |
| http://www.analog.com/static/imported-files/tutorials/MT-046.pdf\\ | http://www.analog.com/static/imported-files/tutorials/MT-046.pdf\\ |
| http://www.analog.com/static/imported-files/application_notes/466359863287538299597392756AN359.pdf\\ | http://www.analog.com/static/imported-files/application_notes/466359863287538299597392756AN359.pdf\\ |
| http://en.wikipedia.org/wiki/Settling_time\\ | [[wp>Settling_time|Settling time]] |
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| Return to Lab Activities [[university:courses:electronics:labs|Table of Contents]] | Return to Lab Activities [[university:courses:electronics:labs|Table of Contents]] |
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