This version is outdated by a newer approved version.
This version (17 May 2015 15:04) is a draft.
Approvals: 0/1The Previously approved version (14 Dec 2012 21:26) is available.
This version (17 May 2015 15:04) is a draft.Approvals: 0/1The Previously approved version (14 Dec 2012 21:26) is available.
This is an old revision of the document!
Table of Contents
Activity 11M. The Source follower (NMOS)
Objective:
To investigate the simple NMOS source follower amplifier also sometimes referred to as the common drain configuration.
Materials:
Analog Discovery Lab hardware
Solder-less breadboard
Jumper wires
1 - 2.2KΩ Resistor (RL)
1 - small signal NMOS transistor (enhancement mode CD4007 or ZVN2110A M1)
Directions:
The breadboard connections are shown in the diagram below. The output of the waveform generator, W1, is connected to the gate terminal of M1. Scope input 1+ (Single Ended) is also connected to W1 output. The drain terminal is connected to the positive (Vp) supply. The source terminal is connected to both the 2.2KΩ load resistor and Scope input 2+ (Single Ended). The other end of the load resistor is connected to the negative (Vn) supply. To measure the input to output error, channel 2 of the scope can be used differentially by connecting 2+ to the gate of M1 and 2- to the source.
Figure 1 Source Follower
Hardware Setup:
The waveform generator should be configured for a 1 KHz Sine wave with 2 volt amplitude and 0 offset. The Single ended input of scope channel 2 (2+) is used to measure the voltage at the source. The Scope configured with channel 1+ connected to display the AWG generator output. When measuring the input to output error, channel 2 of the scope should be connected to display 2+ and 2- differential.
Figure 2 Input, output waveforms
Procedure:
The incremental Gain (Vout /Vin) of the source follower should ideally be 1 but will always be slightly less than 1. The gain is generally given by the following equation:
From the equation we can see that in order to obtain a gain close to one we can either increase RL or decrease rs. We also know that rs is a function of ID and that as ID increases rs decreases. Also from the circuit we can see that ID is related to RL and that as RL increases ID decreases. These two effects work counter to each other in the simple resistive loaded emitter follower. Thus to optimize the gain of the follower we need to explore ways to either decrease rs or increase RL without effecting the other. It is important to remember that in MOS transistors ID = IS ( IG = 0 ).
where K =?nCox/2and ??can be taken as process technology constants.
Looking at the follower in another way, because of the inherent DC shift due to the transistor's Vth, the difference between input and output should be constant over the intended swing. Due to the simple resistive load RL, the drain current ID increases and decreases as the output swings up and down. We know that ID is a (square law) function of VGS In this +2V to -2V swing example the minimum ID=2V/2.2KΩ or 0.91 mA to a maximum ID= 6V/2.2KΩ or 2.7mA. This results in a significant change in VGS. This observation leads us to the first possible improvement in the source follower.
The current mirror from activity 6M is now substituted for the source load resistor to fix the amplifier transistor source current. A current mirror will sink a more or less constant current over a wide range of voltages. This more or less constant current flowing in the transistor will result in a more or less constant VGS. Viewed another way, the very high output resistance of the current source has effectively increased RL while rs remains at a low value set by the current.
Additional Materials:
1 - 3.2KΩ Resistor (use a 1KΩ in series with a 2.2KΩ)
1 - small signal NMOS transistor (M1ZVN2110A)
2 - small signal NMOS transistors (M2, M3CD4007)
Figure 3 Improved Source Follower
Figure 4 Input vs output error for resistor and current source load
Source follower output impedance
Objective:
An important aspect of the source follower is to provide power or current gain. That is to say drive a lower resistance (impedance) load from a higher resistance (impedance) stage. Thus it is instructive to measure the source follower output impedance.
Materials:
1 - 4.7KΩ Resistor
1 - 10KΩ Resistor
1 - small signal NMOS transistor ( M1 CD4007 or ZVN2110A)
Directions:
The circuit configuration below adds a resistor R2 to inject a test signal from AWG1 into the emitter (output) of M1. The input, base of M1, is grounded.
Figure 5 Output impedance test
Hardware Setup:
The waveform generator should be configured for a 1 KHz Sine wave with 1 volt amplitude with the offset set equal to minus the VGS of M1 ( approximately -V ). This injects a +/- 0.1mA (1V/10KΩ) current into M1's source. Scope input 2+ measures the change in voltage seen at the source.
Procedure:
The red line in the plot below shows the measured result with the adjustable resistor set to its minimum, i.e. 0 ohms. The voltage at the emitter actually goes down slightly as the test input goes up, and goes up slightly when the test input goes down. This would indicate that the output resistance of the emitter follower is negative in this case. Why is this happening?
The green line in the plot above shows the measured result with the adjustable resistor set to a value greater than 0 ohms. You should adjust the resistor starting at 0 ohms and increase the value while observing the waveform. It should flatten out as the resistance in the gate increases. The reader should stop at the point where the line has just flattened out and measure the value of the potentiometer. Remember you must remove the pot from the circuit before measuring it. What is the value? Why is that value significant?
The nominal source current in M1 is (Vn - VGS) / 4.7KΩ or 720uA. We can calculate rsfrom this current as ohms. How does this rs compare to the value measured for the potentiometer?
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university/courses/electronics/electronics-lab-11m.1431867895.txt.gz · Last modified: 17 May 2015 15:04 by Doug Mercer