The purpose of this activity is to investigate the operation of the enhancement mode NMOS transistor as a current mirror.
As in all the ALM labs we use the following terminology when referring to the connections to the M1000 connector and configuring the hardware. The green shaded rectangles indicate connections to the M1000 analog I/O connector. The analog I/O channel pins are referred to as CA and CB. When configured to force voltage / measure current -V is added as in CA-V or when configured to force current / measure voltage -I is added as in CA-I. When a channel is configured in the high impedance mode to only measure voltage -H is added as CA-H.
Scope traces are similarly referred to by channel and voltage / current. Such as CA-V , CB-V for the voltage waveforms and CA-I, CB-I for the current waveforms.
ADALM1000 hardware module
2 - small signal NMOS transistors (ZVN2110A or CD4007 NMOS array)
The good way to measure the characteristics of the current mirror is to reuse the same basic configuration that was used in the common source FET curve tracer experiments. Diode connected transistor M1 is connected across the gate and source terminals of M2. Iin will be equal to the Channel A output current. Iout will be the current measured by channel B.
Figure 1 NMOS Current mirror test circuit
In the current mirror configuration, generator Channel A is configured as SIMV (CA-I). The VGS of M1 and M2 will be the measured Channel A voltage (CA-V). The drain voltage is swept using a ramp from Channel B (SVMI) set to 4.5V Max and 0 V Min. The mirror output current is measured by the CB-I current measurement. You can use the X-Y mode displaying CA-I on the X axis (Iin) and CB-I (Iout) on the Y axis to plot the current mirror transfer function. You can use the CA-I - CB-I math waveform to plot the current mirror input to output error and offset. The CB-I/CA-I math waveform can be used to plot the current mirror Iout/Iin current gain.
Two identical transistors with the same gate to source voltage will have the same drain current ID. The second transistor, M2, in effect mirrors the current in the first, M1. Remembering the drain current to gate source voltage relationship for a MOS transistor:
where K =MunCox/2and Lamda can be taken as process technology constants.
Identical transistors by definition have the same W/L and process technology constants. In the simple current mirror, both transistors have the same VGS. Thus, both transistors will have the same ID. Since no current flows in the gate terminal of a FET Iin = Iout.
You are to measure Iin, Rout seen into the drain of M2, the current mirror gain = Iout/Iin and determine the Norton and Thevenin equivalent circuits for this mirror.
Try building a PMOS version of the current mirror from the PMOS devices in the CD4007 array or the ZVP2110A discrete transistors from the Parts Kit. How would you have to modify the circuit figure 1 to measure PMOS transistor?
For Further Reading:
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