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This version (03 Nov 2018 17:16) was approved by dmercer.The Previously approved version (27 Jul 2018 15:26) is available.Diff

Activity 16: Capacitor Based DC-DC Converters

Objective:

The object of this activity is to explore a capacitor based circuit which can produce an output voltage which is higher than the supplied voltage. This class of circuits are referred to as DC to DC converters or boost regulators.

Notes:

As in all the ALM labs we use the following terminology when referring to the connections to the M1000 connector and configuring the hardware. The green shaded rectangles indicate connections to the M1000 analog I/O connector. The analog I/O channel pins are referred to as CA and CB. When configured to force voltage / measure current –V is added as in CA-V or when configured to force current / measure voltage –I is added as in CA-I. When a channel is configured in the high impedance mode to only measure voltage –H is added as CA-H.

Scope traces are similarly referred to by channel and voltage / current. Such as CA-V , CB-V for the voltage waveforms and CA-I , CB-I for the current waveforms.

The circuits used in this Lab activity while generally low current can produce voltages beyond the 0 to 5 V analog input range of the ALM1000. Input voltage divider techniques as discussed in the document on ALM1000 analog inputs will be required. Refer to the document and construct and use input dividers before preforming any of these experiments with the ALM1000.

Concept:

The basic concept of capacitor based DC to DC converter is shown below in figure 1. These are often referred to as “flying capacitor” or “charge-pump” voltage converters. The operation alternates between the two configurations of the switches shown in figure 1. In one, switches S1 and S5 are closed connecting C1 between ground and VIN. In the second, switches S4 and S8 are closed connecting C2 between VIN and VBoost. For the half cycle shown capacitor C1 is charged to the voltage at VIN and VBoost is the sum of the voltage at VIN and the voltage on capacitor C2. For the second half cycle the switches are reversed. Now with S2 and S6 closed C1 is connected between VIN and VBoost. Also switches S3 and S7 will now be closed connecting C2 between ground and VIN. So now we can see that after a few cycles VBoost, the voltage across capacitor C3 will be equal to twice VIN. As you can see the capacitors “fly” back and forth between VIN and VBoost, thus the name “flying capacitor”. One can also see that what is in effect happening is the charge on capacitors C1 and C2 is alternately transferred or pumped onto capacitor C3 charging it up to two times VIN. This action gives rise to the second “charge pump” name.

Figure 1 Capacitor based voltage doubler

We will now replace the ideal switches in the diagram with actual electronic switches. There are a number of possible devices that could be used but the MOS FET transistor is most often used because it can have both a low voltage drop and resistance when turned on. The next diagram shows a direct substitution of NMOS ( S1,S3,S5,S7 ) and PMOS ( S2,S4,S6,S8 ) devices for the switches in the first diagram. It can be noted that switches S1 and S2 form a complementary pair and take the same form as a CMOS inverter logic gate. The other three sets of switches form similar complementary pairs.

Figure 2 CMOS voltage doubler

Materials:

ADALM1000 hardware module
Solder-less breadboard and jumper wire kit
1 – 1 MΩ resistor
1 – 200 KΩ resistor
1 – ZVN2110A NMOS FET ( 2N7000 )
2 – ZVN3310 NMOS FET ( 2N7000 )
1 – ZVP2110A PMOS FET
2 – 74HC04 HEX CMOS Inverters ( CD4007, CD4069 )
1 – LT1054
2 – 10uF capacitors
1 – 220uF capacitor
2 – 1N914 diodes (1N4001 or 1N5819 Schottky diodes)

Additional Equipment:

Small handheld DMM ( optional )
+5 V bench power supply or 4.5 V battery ( optional )

Directions:

Before we build any of the DC-DC converter circuits we need to build an input voltage divider circuit to attenuate or reduce the voltages being measured to a low enough value to fit safely within the 0V to +5V range allowed for the ADALM1000 analog inputs. Build the simple voltage divider shown in figure 3 on one end of your solderless breadboard. A DC offset voltage is supplied from the fixed 5 V supply to allow the ability to measure both positive and negative voltages.

Figure 3, Input voltage divider with buffer op-amp follower

Use the ALICE Desk-top input attenuator gain and offset entry widgets ( figure 4A ) to calibrate the displayed voltage level by connecting the divider input ( end of R1 ) to ground and the fixed +5 V supply on the ADALM1000. Adjust the offset value such that the scope trace displays 0 V with the input grounded. Next adjust the gain value so that the trace displays as +5 V with the input connected to +5 V supply. With R2 = 200 KΩ the gain factor should be around 6 but is actually 7.2 due to the internal 1 MΩ input resistance of the input. You can double check your settings by connecting the input to the +2.5 V supply and the trace should read as 2.5V. You can now safely measure voltages within the range shown in figure 3. Be sure to only use the voltage divider input when measuring voltages in this Lab.

Figure 4A Input Attenuator settings

For this lab you will be mainly making DC measurements but the frequency response of the input divider can also be adjusted. To adjust the compensation settings open the Change Settings screen. Set CHA to SVMI mode and Shape Square. Set Min value to 0.5 and Max to 4.5. Set the Frequency to 500 Hz. With CHB in Hi-Z mode and connected to the voltage divider connect CHA output to the input of the divider. Adjust the CHB compensation TC1, A1 and TC2, A2 until the CHB wave shape is a flat top square wave just like CHA. Something like the settings shown in Figure 4B.

Figure 4B Frequency compensation settings

The software should now be calibrated for using the input divider with CHB.

First DC-DC converter

The breadboard connections for the first version are as shown in figure 5 below. The voltage divider circuit should be connected to measure the voltage at VBoost. (or DMM could be used). The +5V bench power supply or 4.5 V battery should be connected to the Vin node. The digital pulse output drives the input of the first Inverter gate at pin 1. Scope input CA-H through the external resistor divider (see figure 3) is connected to the drain terminal of M1 and scope input CB-H through an external resistor divider is connected to the drain terminal of M2.

Figure 5 NMOS and Diode DC-DC converter

Hardware Setup:

The VClock pulse can be supplied from the Channel A output or the digital pulse source circuit (details below in figure 8) and should generate a 50% duty cycle square wave with at least a 20 KHz output frequency. The input of scope channel CB-V with the external resistor divider is used to measure the waveform seen at the drain of M1 and to measure the waveform seen at the drain of M2 and to measure the VBoost output voltage.

Procedure:

Be sure to start up the digital pulse source output before turning on the +5V bench supply or connecting the 4.5 V battery. The boosted output voltage at node VBoost should be observed and should be approximately equal to 2 times the DC value of the external supply.

Questions:

What is the voltage on VBoost? Why is it not exactly 2 times VIN?

What is the effect of changing the frequency of the digital pulse output? Is there a minimum? or a maximum?

How much current can the circuit supply to a load? Try various resistors as a load.

Is that current affected by the frequency of the digital pulse output?

Calculate the conversion efficiency of the circuit. Ratio of output power (IOUT*VBoost) to input power (IIN* 5V)

Change the value of C1 and C2 and redo the above. How have the results changed?

Connect the other inverters in the 74HC04 package in parallel with INV1 and INV2 in the diagram. What effect do these added drivers have on the results?

Directions:

The breadboard connections for another version are as shown in figure 6 below. A one package of CMOS inverters is used for the upper set of switches (INV1 and INV2) rather than the discrete FETs and diodes. The ground connection of the 74HC04 at pin 7 is connected to the VIN node and the supply connection at pin 14 becomes the VBoost node. The voltage divider input should be connected to measure the voltage at VBoost. The +5V power supply should be connected to the VIN node. The LT1054 is used as both the clock digital pulse source and first driver output for capacitor C1 and drives the input of the Inverter at the gates of NMOS M1 and PMOS M2.

Figure 6 All CMOS Inverter configuration

Figure 7 shows an inverting DC-DC configuration that produces VBoost equal to –VIN. The 74HC04 is connected below ground as shown to produce a VBoost that is equal to –VIN.

Figure 7 Supply voltage inverter.

Digital pulse generator:

What sort of circuit could you make to generate the 100 KHz square wave? There are four additional inverters in the 74HC04 package. The other inverters along with RC delay network, R4 C4 can be configured into a ring oscillator as shown below. The values for R4 and C4 are approximate for 100 KHz and can be adjusted as needed.

Figure 8 square wave oscillator

Questions:

What other types of oscillator circuits might be used to generate the 100 KHz square wave?

For further reading:

http://en.wikipedia.org/wiki/DC-to-DC_converter
http://en.wikipedia.org/wiki/Charge_pump
http://www.analog.com/static/imported-files/data_sheets/ADM660_8660.pdf

Appendix:

Hex inverter Pinouts:

Figure 9 74HC04 and CD4069 share the same package pinouts

CD4007 Pinout:

Figure 10 CD4007 CMOS array pinout

As many as three individual inverters can be built from one CD4007 package. The simplest first one to configure as shown below is by connecting pins 8 and 13 together as the inverter output. Pin 6 will be the input. Be sure to connect pin 14 VDD to power and pin 7 VSS to ground.

Figure 11 CD4007 inverter connections

The second Inverter is made by connecting pin 2 to VDD, pin 4 to VSS, pins 1 and 5 are connected together as the output and with pin 3 as the input.

The third inverter is made by connecting pin 11 to VDD, pin 9 to VSS, pin 12 is the output and pin 10 is the input.

Two of these inverters can be used to construct the inverters needed in figure 5.

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university/courses/alm1k/alm-lab-16.txt · Last modified: 03 Nov 2018 17:16 by dmercer