This version (27 Sep 2023 08:48) was approved by John Joseph.The Previously approved version (28 Jun 2020 17:37) is available.
Table of Contents
Audio Input-Output Modes
This section describes the different types of inputs and outputs which are supported by SigmaStudio for SHARC (ADSP-SC5xx/ADSP-215xx) Target Framework.
Analog\Digital Co-existence
Analog\Digital Co-existence Audio I/O mode supports Analog/Digital Inputs and Analog Outputs.
Routing scheme for ADSP-SC58x\ADSP-2158x\ADSP-SC59x\ADSP-2159x
The routing scheme for Analog\Digital Co-existence mode for ADSP-SC58x\ADSP-2158x\ADSP-SC59x\ADSP-2159x processors is illustrated in Figure below.
The analog data path consisting of CODEC and SPORT’s are configured in TDM mode. The digital S/PDIF path is in I2S mode. ASRC and PCG’s are used by the framework to facilitate this configuration.
Default Audio I/O mode Configuration - Analog\Digital Co-existence for ADSP-SC58x\ADSP-2158x\ADSP-SC59x\ADSP-2159x
The master clock for PCG C is derived from 24.576 MHz which is available through DAI1_PIN03. The bit clock and frame sync for CODEC and the SPORTs are derived from PCG C using appropriate clock and frame sync dividers. By default, PCG C is configured to generate clock and frame sync signals for TDM8 configuration at 48 kHz sample rate. The clock and frame sync from PCG C are also available on DAI0_PIN10 and DAI0_PIN12 respectively. These pins are used for clocking the SPORTs of DAI0.
The master clock for PCG A is derived from 24.576 MHz which is available through DAI0_CRS_PIN03. The bit clock and frame sync for SRC 0 and SPORT used for obtaining the data from S/PDIF are derived from PCG A using appropriate clock and frame sync dividers. SRC 0 is used to de-jitter the S/PDIF recovered clock. By default, PCG A is configured to generate clock and frame sync signals for I2S configuration at 48 kHz sample rate. The clock and frame sync from PCG A are also available on DAI1_PIN11 and DAI1_PIN19 respectively. These pins are used for clocking the SPORTs of DAI1.
Routing Scheme for ADSP SC57x\2157x
The master clock for PCG A and PCG B is derived from 24.576 MHz which is available through DAI0_PIN03. By default, PCG B is configured to generate clock and frame sync signals for TDM8 configuration at 48 kHz sample rate and PCG A is configured to generate clock and frame sync signals for I2S configuration at 48 kHz sample rate.
The bit clock and frame sync for CODEC and SPORTs are derived from PCG B. The bit clock and frame sync for SRC 0 and SPORT used for obtaining the data from S/PDIF are derived from PCG A. SRC 0 is used to de-jitter the S/PDIF recovered clock.
Routing Scheme for SC589 SAM
The master clock for PCG A and PCG B is derived from 12.288 MHz which is available through DAI0_PIN06. By default, PCG B is configured to generate clock and frame sync signals for TDM8 configuration at 48 kHz sample rate and PCG A is configured to generate clock and frame sync signals for I2S configuration at 48 kHz sample rate.
The bit clock and frame sync for CODEC and SPORTs are derived from PCG B. The bit clock and frame sync for SRC 0 and SPORT used for obtaining the data from S/PDIF are derived from PCG A. SRC 0 is used to de-jitter the S/PDIF recovered clock.
Routing Scheme for ADSP 2156x
For the ADSP-2156x processors, the default IO routing is as shown in Figure 9. The master clock for PCG C is derived from 24.576 MHz which is available through DAI1_PIN03. The bit clock and frame sync for CODEC and the SPORTs are derived from PCG C using appropriate clock and frame sync dividers. By default, PCG C is configured to generate clock and frame sync signals for TDM8 configuration at 48 kHz sample rate. The clock and frame sync from PCG C are also available on DAI0_PIN07 and DAI0_PIN19 respectively. These pins are used for clocking the SPORTs of DAI0.
The master clock for PCG A is derived from 24.576 MHz which is available through DAI0_CRS_PIN03. The bit clock and frame sync for SRC 0 and SPORT used for obtaining the data from S/PDIF are derived from PCG A using appropriate clock and frame sync dividers. SRC 0 is used to de-jitter the S/PDIF recovered clock. By default, PCG A is configured to generate clock and frame sync signals for I2S configuration at 48 kHz sample rate. The clock and frame sync from PCG A are also available on DAI1_PIN07 and DAI1_PIN19 respectively. These pins are used for clocking the SPORTs of DAI1.
resources/tools-software/sigmastudiov2/targetintegration/targetapplication/audioiomodes.txt · Last modified: 18 Sep 2023 09:08 by Sakthivel Perumal