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The Register Control windows provides access to the internal registers and core settings for the DSP and IC blocks inserted in the Hardware configuration window.
To access the Register Control window:
The controls and settings available in the Register Control window are different for each Processor (IC/DSP) block, depending on the hardware's capability. Any changes made in the register control window are immediately sent to the hardware when there is an active USB communication channel.
Following is a description of the AD1940 Register Control window. For information about these or other IC register settings, please see the refer to your part's datasheet: www.analog.com/sigmadsp
1. Internal Registers This area lists addresses 2642 - 2646 and their status. As you make changes in the other areas of the window, you'll see the results here. If you know the register bit locations you wish to change, you can change them here as well, and the buttons in the other areas of the window will be updated accordingly.
2. Serial Input - affects the serial-input control register (address 2646), controlling clock polarity and data input modes.
3. Ram Modulo - affects the ram-configuration register (address 2643)
The AD1940/1941 uses a modulo RAM-addressing scheme to allow filters and other blocks to be coded easily without requiring filter data to be explicitly moved during the filtering operation. The default value is 12 where the entire 6144 (6k) RAM is treated as modulo memory with auto-incrementing address-offset registers. Each LSB of this register corresponds to 512 RAM locations. A modulo value of 11 would give you 5632 datawords of modulo memory and 512 in a non-modulo portion.
4. DSP Core - affects DSP core control register (address 2642)
The controls in this register set the operation of the AD1940/-41's DSP core.
5, 6. Serial Outputs 1 (address 2644) and 2 (address 2645) The output control registers give the user control of clock polarities, clock frequencies and types, and data format. In all modes except for the right-justified ones (MSB delayed by 8, 12, or 16), the serial port accepts an arbitrary number of bits up to 24. Extra bits will not cause an error but will be truncated internally. Proper operation of the right-justified modes requires the LSB to align with the edge of the LRCLK.
Wordlength (Bits 1:0) - These bits set the length of the output dataword. Options are 16, 20, or 24 bits.
MSB Position (Bits 4:2) - These three bits set the position of the MSB of data with respect to the LRCLK edge. The data output of the AD1940/-41 is always MSB first.
Frame Synch Type (Bit 6) - This bit sets the type of signal on the LRCLK_OUTx pins. When set to 0, the signal is a clock with a 50% duty cycle; when set to 1, the signal is a pulse with a duration of one bit clock at the beginning of the data frame.
Frame Synch Frequency (Bits 8:7) - When the output port is used as a clock master, these bits set the frequency of the output LRCLK, which is divided down from the internal 73.728 MHz core clock.
BCLK frequency (Bits 10:9) - When the output port is being used as a clock master, these bits set the frequency of the output bit clock, which is divided down from the internal 73.728 MHz core clock.
Master/Slave (Bit 11) - This bit sets whether the output port is a clock master or slave. The default setting is slave; on powerup, Pins BCLK_OUTx and LRCLK_OUTx are set as inputs until this bit is set to 1, at which time they become clock outputs.
BCLK Polarity (Bit 12) - This bit controls on which edge of the bit clock the output data are clocked: on the falling edge of BCLK_OUTx when this bit is set to 0, and on the rising edge when it's set at 1.
LRCLK Polarity (Bit 13) - When set to 0, the left-channel data are clocked when LRCLK is low, and the right data clocked when LRCLK is high. When set to 1, this is reversed.
Link TDM Streams (Bit 14, Serial Output Control Register 1) - When this bit is set to 1, the TDM output streams a linked to output a single 16-channel stream on SDATA_OUT0. When set to 0, TDM data are output on two independent 8-channel streams, on pins SDATA_OUT0 and SDATA_OUT4.
Dither-Enable (Bit 15) - Setting this bit to 1 enables dither on the appropriate channels.