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| resources:tools-software:linux-drivers:jesd204:axi_jesd204_rx [08 Apr 2022 15:17] – fix link Antoniu Miclaus | resources:tools-software:linux-drivers:jesd204:axi_jesd204_rx [15 Nov 2023 11:39] (current) – [Sysfs Interface] Michael Hennerich |
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| **Reading the device/link status:** | **Reading the device/link status:** |
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| | ^ What ^ Comment ^ |
| | | Link is [enabled%%|%%disabled] | Link state indicator. In case link state is disabled, that either means the link was never enabled or that an error occurred and the FSM rolled back and disabled the link. In the jesd204-fsm case this can be prevented by using the ''jesd204-ignore-errors;'' devicetree property when placed in the jesd204-fsm jesd204-top-device node. | |
| | | Link status | Depending on the encoding JESD204B/C 8B10B/64B66B there can be different values ''RESET'', ''WAIT'', ''CGS'', ''ILAS'', etc., ''DATA'' Please see link layer documentation for the state machine: [[resources:fpga:peripherals:jesd204:axi_jesd204_rx|JESD204B/C Link Receive Peripheral]] \ [[resources:fpga:peripherals:jesd204:axi_jesd204_tx|JESD204B/C Link Transmit Peripheral]] In general ''DATA'' is the desired state indicating proper operation. | |
| | | SYNC is [asserted%%|%%deasserted] (8B10B only) | State of the external ''SYNC'' signal. | |
| | | SYSREF captured: [Yes%%|%%No] (Subclass 1 only) | Yes indicates that a ''SYSREF'' pulse was captured. | |
| | | SYSREF alignment error: [Yes%%|%%No] (Subclass 1 only) | Yes indicates that a ''SYSREF'' event has been observed which was unaligned, in regards to the ''LMFC/LEMC'' period, to a previously recorded ''SYSREF'' event. | |
| | | Lane rate | The ''SERDES'' lane rate / bit clock. | |
| | | [LMFC%%|%%LEMC] rate | Frequency of the internal local multiframe clocks (''LMFC'')/ local-multiblock-clock (''LEMC''). | |
| | | Lane rate / [40%%|%%66] | Is equal to the desired ''Link Clock'' frequency. | |
| | | Reported Link Clock | Is the ''Link Clock'' frequency which is reported by the common clock framework. If this rate is different from the desired ''Link Clock'' frequency, there is likely a problem. For example the clock provider wasn’t able to set the desired value. | |
| | | Measured Link Clock | Is the measured ''Link Clock'', using a frequency counter inside the Link Layer Peripheral. For proper operation desired, reported and measured frequency must match. | |
| | | Desired Device Clock | In case this value is different from the Desired ''Link Clock'', this indicates Dual Clock Operation required by the Gearbox. Please see Gearbox/Dual Clock Operation in the Link Layer Peripheral documentation: [[resources:fpga:peripherals:jesd204:axi_jesd204_rx|JESD204B/C Link Receive Peripheral]] \ [[resources:fpga:peripherals:jesd204:axi_jesd204_tx|JESD204B/C Link Transmit Peripheral]] The ''Device Clock'' is typically generated by the clock provider which also provides ''SYSREF''. | |
| | | Reported Device Clock | Is the ''Device Clock'' frequency which is reported by the common clock framework. If this rate is different from the desired ''Device Clock'' frequency, there is likely a problem. For example the clock provider wasn’t able to set the desired value. | |
| | | Measured Device Clock | Is the measured ''Device Clock'', using a frequency counter inside the Link Layer Peripheral. For proper operation desired, reported and measured frequency must match. | |
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| <WRAP box bggreen><wrap info>This specifies any shell prompt running on the target</wrap> | <WRAP box bggreen><wrap info>This specifies any shell prompt running on the target</wrap> |
