This version is outdated by a newer approved version.
This version (05 Dec 2019 13:30) is a draft.
Approvals: 0/1The Previously approved version (06 May 2019 14:30) is available.
This version (05 Dec 2019 13:30) is a draft.Approvals: 0/1The Previously approved version (06 May 2019 14:30) is available.
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Table of Contents
HMC7044 Clock Jitter Attenuator with JESD204B Linux Driver
Supported Devices
Description
HMC7044 is a high performance, dual-loop, integer-N jitter attenuator capable of performing reference selection and generation of ultralow phase noise frequencies for high speed data converters with either parallel or serial (JESD204B type) interfaces.
The HMC7043 is a high performance clock buffer for the distribution of ultralow phase noise references for high speed data converters with either parallel or serial (JESD204B type) interfaces.
This is a Linux industrial I/O (IIO) subsystem driver, targeting serial interface PLL Synthesizers. The industrial I/O subsystem provides a unified framework for drivers for many different types of converters and sensors using a number of different physical interfaces (i2c, spi, etc). See IIO for more information.
Source Code
Status
| Source | Mainlined? |
|---|---|
| drivers/iio/frequency/hmc7044.c | No |
Files
| Function | File |
|---|---|
| driver | drivers/iio/frequency/hmc7044.c |
| Documentation | Documentation/devicetree/bindings/iio/frequency/hmc7044.txt |
Enabling the driver
Configure kernel with “make menuconfig” (alternatively use “make xconfig” or “make qconfig”)
The HMC7044 Driver depends on CONFIG_SPI
Linux Kernel Configuration
Device Drivers --->
<*> Industrial I/O support --->
Frequency Synthesizers DDS/PLL --->
Clock Generator/Distribution --->
<*> Analog Devices HMC7044 Clock Jitter Attenuator with JESD204B
Adding a device tree entry
Available properties
Required properties:
- compatible: Should be “adi,hmc7044”.
- reg: SPI chip select number.
- spi-max-frequency: Max SPI frequency to use (⇐ 10000000).
- adi,pll1-clkin-frequencies: An array of 4 elements, each representing the frequency of CLKINx PLL1 reference input (CLKIN0, CLKIN1, CLKIN2, CLKIN3).
- adi,vcxo-frequency: The frequency of the VCXO.
- adi,pll2-output-frequency: The desired output frequency of the PLL2.
- adi,gpi-controls: An array of 4 elements (each corresponding to GPI1, GPI2, GPI3 and GPI4, respectively), representing the GPI selection (Bits [4:1]) and the GPI enable bit ([0]) - see registers 0x0046, 0x0047, 0x0048, 0x0049.
- adi,gpo-controls: An array of 4 elements (each corresponding to GPO1, GPO2, GPO3 and GPO4, respectively), representing the GPO selection (Bits [7:2]), the GPO mode (Bit [1]) and the GPO enable bit ([0]) - see registers 0x0050, 0x0051, 0x0052, 0x0053.
- clock-output-names: An array of 14 elements, representing the names of the output clocks.
Optional properties:
- adi,pll1-loop-bandwidth-hz: The PLL1 loop bandwidth. If this is not specified, 200 will be used by default.
- adi,sysref-timer-divider: This sets the internal beat frequency of the master timer, which controls synchronization and pulse generator events. It should be set to a submultiple of the lowest output SYSREF frequency, no faster than 4 MHz. If this is not specified, 1024 will be used by default.
- adi,pulse-generator-mode: Pulse Generator Mode Selection [Bits 2:0] - see register 0x005A. If this is not specified, 0 will be used by default.
- adi,clkin0-buffer-mode: CLKIN0 Input Buffer Control, for specifying the Input Buffer Mode (Bits [4:1]) and the Buffer enable bit ([0]) - see register 0x000A. If this is not specified, 0 will be used by default.
- adi,clkin1-buffer-mode: CLKIN1 Input Buffer Control, for specifying the Input Buffer Mode (Bits [4:1]) and the Buffer enable bit ([0]) - see register 0x000B. If this is not specified, 0 will be used by default.
- adi,clkin2-buffer-mode: CLKIN2 Input Buffer Control, for specifying the Input Buffer Mode (Bits [4:1]) and the Buffer enable bit ([0]) - see register 0x000C. If this is not specified, 0 will be used by default.
- adi,clkin3-buffer-mode: CLKIN3 Input Buffer Control, for specifying the Input Buffer Mode (Bits [4:1]) and the Buffer enable bit ([0]) - see register 0x000D. If this is not specified, 0 will be used by default.
- adi,oscin-buffer-mode: OSCIN Input Buffer Control, for specifying the Input Buffer Mode (Bits [4:1]) and the Buffer enable bit ([0]) - see register 0x000E. If this is not specified, 0 will be used by default.
Adding channels
Channels can be specified using child nodes. The following properties are applicable to them:
- reg: The identifier of the channel.
- adi,extended-name: Descriptive channel name.
- adi,divider: Channel divider. The divider supports even divide ratios from 2 to 4094. The supported odd divide ratios are 1, 3, and 5.
- adi,driver-mode: Output driver mode. Must be one of:
- 0 - CML mode,
- 1 - LVPECL mode,
- 2 - LVDS mode,
- 3 - CMOS mode.
- adi,high-performance-mode-disable:Disables the high performance mode
- adi,startup-mode-dynamic-enable:Enables pulse generator mode (default mode is asynchronous)
- adi,force-mute-enable: When not generating pulses in dynamic mode the output is forced to logic-0
- adi,coarse-digital-delay: Adjusts the phase of the divider signal by up to 17 1/2 cycles of the VCO
- adi,fine-analog-delay: Adjusts the delay of the divider signal in 24 fine delay steps. Step size = 25 ps.
- adi,output-mux-mode: Configures the output mux selection:
- 0 = divider channel (default)
- 1 = analog delay
- 2 = other channel of pair
- 3 = input VCO clock.
Device tree example
The following example instanciates the hmc7044 driver for a HMC7044 device connected on the SPI bus to the chip-select line 0.
hmc7044: hmc7044@0 {
compatible = "adi,hmc7044";
reg = <0>;
spi-max-frequency = <10000000>;
adi,pll1-clkin-frequencies = <122880000 0 0 0>;
adi,pll1-loop-bandwidth = <200>;
adi,vcxo-frequency = <122880000>;
adi,pll2-output-frequency = <2949120000>;
adi,sysref-timer-divider = <1024>;
adi,pulse-generator-mode = <0>;
adi,clkin0-buffer-mode = <0x15>;
adi,oscin-buffer-mode = <0x15>;
adi,gpi-controls = <0x00 0x00 0x00 0x00>;
adi,gpo-controls = <0x1f 0x2b 0x00 0x00>;
clock-output-names = "hmc7044_out0", "hmc7044_out1", "hmc7044_out2",
"hmc7044_out3", "hmc7044_out4", "hmc7044_out5",
"hmc7044_out6", "hmc7044_out7", "hmc7044_out8",
"hmc7044_out9", "hmc7044_out10", "hmc7044_out11",
"hmc7044_out12", "hmc7044_out13";
hmc7044_c2: channel@2 {
reg = <2>;
adi,extended-name = "DAC_CLK";
adi,divider = <1>;
adi,driver-mode = <1>;
};
hmc7044_c3: channel@3 {
reg = <3>;
adi,extended-name = "DAC_SYSREF";
adi,divider = <512>;
adi,driver-mode = <1>;
};
hmc7044_c12: channel@12 {
reg = <12>;
adi,extended-name = "FPGA_CLK";
adi,divider = <8>;
adi,driver-mode = <2>;
};
hmc7044_c13: channel@13 {
reg = <13>;
adi,extended-name = "FPGA_SYSREF";
adi,divider = <512>;
adi,driver-mode = <2>;
};
};
resources/tools-software/linux-drivers/iio-pll/hmc7044.1575549057.txt.gz · Last modified: 05 Dec 2019 13:30 by Michael Hennerich