Wiki

Analog Devices Wiki

English
English
简体中文
简体中文
日本語
日本語
Руccкий
Руccкий

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Next revision		Previous revision
resources:tools-software:linux-drivers:iio-pll:hmc7044 [11 Jul 2018 16:11] – created Dragos Bogdanresources:tools-software:linux-drivers:iio-pll:hmc7044 [22 May 2023 13:03] (current) – [Files] Michael Hennerich
Line 4: Line 4:
  
   * [[adi>HMC7044]]   * [[adi>HMC7044]]
 +  * [[adi>HMC7043]]
  
 ===== Description ===== ===== Description =====
  
 HMC7044 is a high performance, dual-loop, integer-N jitter attenuator capable of performing reference selection and generation of ultralow phase noise frequencies for high speed data converters with either parallel or serial (JESD204B type) interfaces. HMC7044 is a high performance, dual-loop, integer-N jitter attenuator capable of performing reference selection and generation of ultralow phase noise frequencies for high speed data converters with either parallel or serial (JESD204B type) interfaces.
 +
 +The HMC7043 is a high performance clock buffer for the distribution of ultralow phase noise references
 +for high speed data converters with either parallel or serial (JESD204B type) interfaces. 
  
 This is a Linux industrial I/O ([[software:linux:docs:iio:iio|IIO]]) subsystem driver, targeting serial interface PLL Synthesizers. This is a Linux industrial I/O ([[software:linux:docs:iio:iio|IIO]]) subsystem driver, targeting serial interface PLL Synthesizers.
Line 18: Line 22:
  
 ^ Source ^ Mainlined? ^ ^ Source ^ Mainlined? ^
-| [[linux.github>altera_4.9?drivers/iio/frequency/hmc7044.c|drivers/iio/frequency/hmc7044.c]] | No |+| [[linux.github>master?drivers/iio/frequency/hmc7044.c|drivers/iio/frequency/hmc7044.c]] | No |
  
 ===== Files ===== ===== Files =====
 ^ Function ^ File ^ ^ Function ^ File ^
-| driver | [[linux.github>altera_4.9?drivers/iio/frequency/hmc7044.c | drivers/iio/frequency/hmc7044.c]] | +| driver | [[linux.github>master?drivers/iio/frequency/hmc7044.c | drivers/iio/frequency/hmc7044.c]] | 
-| Documentation | [[linux.github>altera_4.9?Documentation/devicetree/bindings/iio/frequency/hmc7044.txt | Documentation/devicetree/bindings/iio/frequency/hmc7044.txt]] |+| Documentation | [[linux.github>master?Documentation/devicetree/bindings/iio/frequency/hmc7044.txt | Documentation/devicetree/bindings/iio/frequency/hmc7044.txt]] |
  
 ====== Enabling the driver ====== ====== Enabling the driver ======
Line 40: Line 44:
              Frequency Synthesizers DDS/PLL  --->               Frequency Synthesizers DDS/PLL  ---> 
                  Clock Generator/Distribution  --->                  Clock Generator/Distribution  --->
-                 <*>  Analog Devices HMC7044 Clock Jitter Attenuator with JESD204B+                 <*>  Analog Devices HMC7044, HMC7043 Clock Jitter Attenuator with JESD204B
  
 </code> </code>
Line 80: Line 84:
     * 2 - LVDS mode,     * 2 - LVDS mode,
     * 3 - CMOS mode.     * 3 - CMOS mode.
 +
 +  * **adi,high-performance-mode-disable**:Disables the high performance mode
 +  * **adi,startup-mode-dynamic-enable**:Enables pulse generator mode (default mode is asynchronous)
 +  * **adi,force-mute-enable**: When not generating pulses in dynamic mode the output is forced to logic-0
 +  * **adi,coarse-digital-delay**:  Adjusts the phase of the divider signal by up to 17 1/2 cycles of the VCO
 +  * **adi,fine-analog-delay**: Adjusts the delay of the divider signal in 24 fine delay steps. Step size = 25 ps.
 +  * **adi,output-mux-mode**: Configures the output mux selection:
 +    * 0 = divider channel (default) 
 +    * 1 = analog delay
 +    * 2 = other channel of pair
 +    * 3 = input VCO clock.
  
 ==== Device tree example ==== ==== Device tree example ====
resources/tools-software/linux-drivers/iio-pll/hmc7044.1531318268.txt.gz · Last modified: 11 Jul 2018 16:11 by Dragos Bogdan

Page Tools