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resources:tools-software:linux-drivers:iio-dds:axi-dac-dds-hdl [12 Apr 2019 10:38] – [Files] Michael Hennerich | resources:tools-software:linux-drivers:iio-dds:axi-dac-dds-hdl [22 Nov 2023 10:08] (current) – Add support for AD9783 iulia Moldovan | ||
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===== Supported Devices ===== | ===== Supported Devices ===== | ||
* [[adi> | * [[adi> | ||
+ | * [[adi> | ||
* [[adi> | * [[adi> | ||
* [[adi> | * [[adi> | ||
+ | * [[adi> | ||
* [[adi> | * [[adi> | ||
* [[adi> | * [[adi> | ||
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* [[adi> | * [[adi> | ||
* [[adi> | * [[adi> | ||
- | + | * [[adi> | |
- | ===== Supported Boards ===== | + | ===== Supported Boards ===== |
This driver supports the\\ | This driver supports the\\ | ||
* [[resources/ | * [[resources/ | ||
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* [[resources/ | * [[resources/ | ||
* [[resources/ | * [[resources/ | ||
- | * [[resources/ | + | * [[resources/ |
+ | * [[resources: | ||
* [[resources/ | * [[resources/ | ||
+ | * [[resources: | ||
* [[resources/ | * [[resources/ | ||
* [[resources/ | * [[resources/ | ||
+ | * [[: | ||
+ | * [[: | ||
* [[resources/ | * [[resources/ | ||
+ | * [[resources: | ||
* [[resources: | * [[resources: | ||
+ | ===== Supported HDL Cores ===== | ||
+ | |||
+ | * [[resources: | ||
+ | * [[resources: | ||
+ | * [[resources: | ||
+ | * [[resources: | ||
+ | * [[resources: | ||
+ | * [[: | ||
+ | |||
+ | ===== Sub device Documentation (linked mode) ===== | ||
+ | |||
+ | * [[resources: | ||
===== Description ===== | ===== Description ===== | ||
- | The AXI DAC DDS HDL driver is the driver for the HDL interface | + | The AXI DAC DDS HDL driver is the driver for various |
+ | |||
+ | This driver is independent from the physical layer. So it's being used with CMOS or LVDS type interfaces or the [[resources: | ||
+ | |||
+ | There are basically two use case scenarios for this driver, in which this driver controls only the HDL/FPGA transport layer capture core. This mode is called '' | ||
+ | The Linux common clock framework is utilized so that this driver knows the sampling frequency of the connected converter DAC device. | ||
+ | Alternatively this driver can also be used in a '' | ||
+ | Finally both the HDL core platform device together with the converter SPI device will register a common IIO device, which will then exhibit a common set of attributes and channels. | ||
+ | The converter SPI device driver is handled in a separate source file, which can be found in the same directory this driver exists. The device tree phandle “spibus-connected” is used to connect the AXI-DAC driver with the SPI control driver. | ||
+ | |||
+ | Sometimes there is a common HDL/FPGA transport layer core, which handles both RX/TX or ADC/DMA. | ||
+ | This single physical core is then handled by two independent IIO drivers each for one transport data direction. | ||
+ | It’s physical address register space is then also split or divided, typically spaced by 0x4000. | ||
+ | A good example for this case is the [[resources: | ||
+ | |||
+ | |||
+ | The HDL/FPGA transport layer capture core driver portion implements a polyphase dual tone DDS core per channel together with an DMA based waveform buffer mechanism. | ||
+ | The buffer can be filled by arbitrary data, which is then typically cyclically repeated or used in a streaming fashion. | ||
- | This driver implements a polyphase dual tone DDS core per channel together with an waveform buffer mechanism. | ||
- | The buffer can be filled by arbitrary data, which is then typically cyclically repeated. | ||
{{ : | {{ : | ||
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^ Source | ^ Source | ||
- | | [[linux.github> | + | | [[linux.github> |
===== Files ===== | ===== Files ===== | ||
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* **compatible**: | * **compatible**: | ||
* adi, | * adi, | ||
+ | * adi, | ||
* adi, | * adi, | ||
- | * adi,axi-ad9739a-8.00.b | + | * adi,axi-ad9162-1.0 |
+ | * adi, | ||
* adi, | * adi, | ||
* adi, | * adi, | ||
* adi, | * adi, | ||
* adi, | * adi, | ||
- | * adi,axi-ad9162-1.0 | + | * adi,axi-ad9739a-8.00.b |
+ | * adi, | ||
+ | * adi, | ||
* **reg**: Base address and register area size. This parameter expects a register range. | * **reg**: Base address and register area size. This parameter expects a register range. | ||
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</ | </ | ||
+ | |||
+ | === External synchronization === | ||
+ | |||
+ | The [[resources: | ||
+ | This feature can also synchronize between the [[resources: | ||
+ | |||
+ | There are two device attributes which allows controlling this feature: | ||
+ | '' | ||
+ | later returns the available modes which depend on HDL core synthesis | ||
+ | parameters. The options are explained below. Reading ' | ||
+ | returns either ' | ||
+ | signal or ' | ||
+ | |||
+ | * '' | ||
+ | |||
+ | * '' | ||
+ | |||
+ | * '' | ||
+ | | ||
+ | == Example: == | ||
+ | |||
+ | <WRAP box bggreen>< | ||
+ | < | ||
+ | root@analog:/ | ||
+ | **arm disarm trigger_manual** | ||
+ | root@analog:/ | ||
+ | **disarm** | ||
+ | root@analog:/ | ||
+ | root@analog:/ | ||
+ | **arm** | ||
+ | root@analog:/ | ||
+ | root@analog:/ | ||
+ | **disarm** | ||
+ | </ | ||
+ | |||
+ | |||
===== Buffer management ===== | ===== Buffer management ===== | ||