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APPENDIX D: Building ADSP-2156x Project
To build the ADSP-2156x project from the SS Plus installer path: “C:\Analog Devices\SigmaStudioPlus-Rel1.2.0\Target\Examples\Demo\ADSP-2156x\ADSP-21569\SS_App_Core1”, following steps need to be followed.
Import the project into CCES
Open “Properties” by right clicking on the project and navigate to “C/C++ Build → Settings”
Remove the macro “ADSP_21569_SOM” from the CrossCore Sharc C/C++ Compiler/Preprocessor Menu as shown in Figure 82.

To provide BCLK and Frame Sync to A2B transceiver, navigate to “system.svc” in the project and open “Signal Routing Unit”.
Under “DAI0 Pin Buffer” following changes need to be made.
DAI0_PB03_I which is routed to PCG0_CRS_CLKC_O by default should be routed removed and
PCG0_CLKA_O should be added. Final configuration is shown in Figure 83.

DAI0_PB04_I which is routed to PCG0_CRS_FSC_O by default should be routed removed and
PCG0_FSA_O should be added. Final configuration is shown in

In the file “C:\Analog Devices\CrossCore Embedded Studio 2.10.0\SHARC\include\drivers\sport\ adi_sport_2156x.h”, the value of
ADI_SPORT_BLOCKING_MODE must be set to “1u” as shown in Figure 85.

Once these changes are made, build the project and copy the generated .dxe file to «A2B plugin for SigmaStudio+ installation path»\Target\Utility\LDR folder.
Use “LDR_gen.bat” script available in «A2B plugin for SigmaStudio+ installation path»\Target\Utility folder to generate the LDR and “Flash_LDR.bat” to flash the updated LDR to
ADSP-2156x eval board.