This version is outdated by a newer approved version.
This version (13 Apr 2012 10:39) was approved by Padraic O Reilly.The Previously approved version (12 Apr 2012 15:43) is available.
This version (13 Apr 2012 10:39) was approved by Padraic O Reilly.The Previously approved version (12 Apr 2012 15:43) is available.This is an old revision of the document!
Table of Contents
AD5686R/AD5685R/AD5684R Quick Start Guide
Quad, 16-/14-/12-Bit, Voltage Output, nanoDAC+® with a 2 ppm/ºC Reference, SPI Interface
Features
- High relative accuracy (INL): ±2 LSB maximum (16-bit AD5686R)
- Low drift 2.5 V on-chip reference: 2ppm/°C typical temperature coefficient
- Tiny 3 mm × 3 mm 16-lead LFCSP or 16-lead TSSOP package
- Total Unadjusted Error (TUE): 0.1 % of FSR max
- Offset error: 1.5 mV maximum
- Gain error: 0.1% of FSR maximum
- High drive capability: 20 mA, 0.5 V from supply rails
- User selectable gain of 1 or 2 (GAIN pin)
- Reset to zero scale or midscale (RSTSEL pin)
- 1.8 V logic compatibility
- 50 MHz SPI interface
- 2.7 V to 5.5 V power supply
- −40°C to +105°C temperature range
Pin Configurations
Table 1. Function Descriptions for Quick Start
| Mnemonic | Description |
|---|---|
| VOUTA | Analog Output Voltage from DAC A. |
| VOUTB | Analog Output Voltage from DAC B. |
| VOUTC | Analog Output Voltage from DAC C. |
| VOUTD | Analog Output Voltage from DAC D. |
| SYNC | Connect to serial interface. |
| SCLK | Connect to serial interface. |
| SDIN | Connect to serial interface. |
| VREF | No connect. |
| VDD | Connect to 5 V supply. Decouple with 10 μF and 0.1 μF capacitors. |
| GND | Connect to ground. |
| LDAC | Tie low. |
| RSTSEL | Tie to GND to power up to zero scale. |
| GAIN | Tie to GND. DAC outputs have a span from 0 V to VREF. |
| RESET | Tie high. |
| VLOGIC | Connect to serial interface supply voltage. |
Shift Register Contents
Table 2. Command Definitions
| Command | Description | |||
|---|---|---|---|---|
| C3 | C2 | C1 | C0 | |
| 0 | 0 | 0 | 0 | No operation |
| 0 | 0 | 0 | 1 | Write to Input Register n (Dependent on LDAC) |
| 0 | 0 | 1 | 0 | Update DAC Register n with contents of Input Register n |
| 0 | 0 | 1 | 1 | Write to and update DAC Channel n |
| 0 | 1 | 0 | 0 | Power down/power up DAC |
| 0 | 1 | 0 | 1 | Hardware LDAC mask register |
| 0 | 1 | 1 | 0 | Software reset(power-on reset) |
| 0 | 1 | 1 | 1 | Internal reference setup register |
| 1 | 0 | 0 | 0 | Set up DCEN register (daisy-chain enable) |
| 1 | 0 | 0 | 1 | Set up readback register (readback enable) |
| 1 | 0 | 1 | 0 | Reserved |
| … | … | … | … | Reserved |
| 1 | 1 | 1 | 1 | Reserved |
Transfer Function
where:
D is the decimal equivalent.
N is the number of bits.
Simple Write: Example 1
To update Channel A, write the following over the serial interface: 0001 XXX1 1000000000000000
(four command bits, four address bits, 16 data bits for the AD5686R).
This updates Channel A to midscale. GAIN = 1, VOUTA = 1.25 V.
This updates Channel A to midscale. GAIN = 1, VOUTA = 1.25 V.
Simple Write: Example 2
To update Channel B, write the following over the
serial interface: 0001 XX1X 1000000000000000.
This updates Channel B to midscale. GAIN = 1, VOUTB = 1.25 V.
This updates Channel B to midscale. GAIN = 1, VOUTB = 1.25 V.
Simple Write: Example 3
To update both Channel A and Channel B, write the following over the serial interface:
0001 XX11 1111111111111111. This updates both channels to full scale. GAIN = 1, VOUTB = 2.5 V, VOUTA = 2.5 V.
resources/quick-start/ad5686r.1334306351.txt.gz · Last modified: 13 Apr 2012 10:39 by Padraic O Reilly