This version (09 Mar 2021 21:40) was approved by Dragos Bogdan.The Previously approved version (29 Mar 2013 11:00) is available.Diff

Quick Start Guide

The bit file provided in the project *.zip file combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system.

Required Hardware

Required Software

  • Xilinx 13.2 Design Suite (contains ISE, XPS, SDK and ChipScope Pro).
  • A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.

Running Demo (SDK) Program

If you are not familiar with LX9 and/or Xilix tools, please visit
products/boards-and-kits/AES-S6MB-LX9.htm for details.

To begin, connect the PmodGYRO2 to J5 connector of LX9 board, pins 7 to 12. You must use an extension cable or the Pmod-TPH (Digilent). Afterwards connect PmodACL to connector J4 of the LX9 Board (see image below).

Connecting Pmods to LX-9 MicroBoard

Start IMPACT, and double click “Boundary Scan”. Right click and select Initialize Chain. The program should recognize the Spartan 6 device (see screenshot below). Program the FPGA using the download.bit file provided in the project *.zip archive, located in the “sw” folder (../adxrs453_adxl345/sw/download.bit).

Programming FPGA in IMPACT

Start a Hyperterminal program (Tera Term, puTTy, etc.), select the proper COM Port (look for the COM Port named Silicon Labs CP210x USB to UART Bridge in Windows Device Manager). Select 57600 Baud Rate and Odd Parity. You should start seeing messeges in the Terminal Window, displayed on 4 columns, representing the rotation of the board in Degrees per Second, and the acceleration in g on each axis.

Messeges displayed in the terminal window

On the LX-9 MicroBoard D10 and D9 display the Tap/Double Tap status. If you tap the device once, D10 will turn on for a short period of time. If you double tap the device, D10 and D9 will both turn on at the same time.

  • Connecting the PmodGYRO2 must be done with an extension cable or a PmodTPH.
  • Connecting the PmodACL to the board with an extension cable provides ease of use.
  • UART must be set to 57600 baudrate.


resources/fpga/xilinx/pmod/adxrs453_adxl345_lx9.txt · Last modified: 09 Jan 2021 00:57 by Robin Getz