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resources:fpga:xilinx:pmod:ad7193 [08 Feb 2012 09:20] – created Alexandru Tofan | resources:fpga:xilinx:pmod:ad7193 [30 Sep 2013 13:19] – [Functional Description] Alexandru.Tofan | ||
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- | + | ====== AD7193 Pmod Xilinx | |
- | + | ||
- | ====== AD7193 | + | |
===== Introduction ===== | ===== Introduction ===== | ||
- | The [[adi> | + | The [[adi> |
The device can be configured to have four differential inputs or eight pseudo differential inputs. The on-chip channel sequencer allows several channels to be enabled simultaneously, | The device can be configured to have four differential inputs or eight pseudo differential inputs. The on-chip channel sequencer allows several channels to be enabled simultaneously, | ||
- | **HW Platform(s): | + | **HW Platform(s): |
- | **System:** Microblaze, AXI, UART \\ | + | * [[http:// |
+ | | ||
+ | | ||
===== Quick Start Guide ===== | ===== Quick Start Guide ===== | ||
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==== Required Hardware ==== | ==== Required Hardware ==== | ||
- | * LX9 microboard | + | * [[http:// |
- | * Pmod-AD5 | + | * [[http:// |
+ | * [[http:// | ||
+ | * [[http:// | ||
==== Required Software ==== | ==== Required Software ==== | ||
- | * Xilinx ISE 13.2 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). | + | * Xilinx ISE 14.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). |
- | * A UART terminal (Tera Term/ | + | * A UART terminal (Tera Term/ |
==== Running Demo (SDK) Program ==== | ==== Running Demo (SDK) Program ==== | ||
- | <note tip>If you are not familiar with LX9 and/or Xilix tools, please visit\\ [[http:// | + | <WRAP center round tip 80%>If you are not familiar with LX9 and/or Xilix tools, please visit\\ [[http:// |
- | </note> | + | If you are not familiar with Nexys™3 and/or Xilix tools, please visit\\ [[http:// |
- | Extract the project from the archive file (AD7193.zip) to the location | + | If you are not familiar with ZedBoard and/or Xilix tools, please visit\\ [[http:// |
- | To begin, connect the Pmod-AD5 to J5 connector of LX9 board, pins 1 to 6 (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board. | + | ==== Avnet LX9 MicroBoard Setup ==== |
- | {{: | + | Extract the project from the archive file (AD7193_< |
- | Start IMPACT, and double click " | + | To begin, connect |
- | {{: | + | {{: |
- | If programming was successful, you should be seeing messages appear on the terminal window as shown in the figure below. After programming the AD7193, the program will display voltage values for all 8 inputs referenced to AINCOM. | + | ==== Digilent Nexys™3 Spartan-6 FPGA Board ==== |
- | {{: | + | Extract the project from the archive file (AD7193_< |
+ | To begin, connect the PmodAD5 to JA connector of Nexys™3 board, pins JA1 to JA6 (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board, one for programming (Digilent USB device) and one for the UART terminal (FT232R USB UART). | ||
+ | |||
+ | {{: | ||
+ | |||
+ | ==== Avnet ZedBoard ==== | ||
+ | |||
+ | To begin, connect the PmodAD5 to JD connector of ZedBoard (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board, one for programming (Digilent USB device) and one for the UART terminal (FT232R USB UART). | ||
+ | |||
+ | {{: | ||
+ | |||
+ | ==== FPGA Configuration for Nexys3 and LX-9 MicroBoard ==== | ||
+ | |||
+ | Start IMPACT, and double click " | ||
+ | |||
+ | {{: | ||
+ | |||
+ | ==== FPGA Configuration for ZedBoard ==== | ||
+ | |||
+ | Run the **download.bat** script from the " | ||
+ | The script will automatically configure the ZYNQ SoC and download the *.elf file afterwards. | ||
+ | |||
+ | <WRAP center round tip 80%> | ||
+ | If the download script fails to run, modify the Xilinx Tools path in **download.bat** to match your Xilinx Installation path. | ||
+ | </ | ||
+ | |||
+ | If programming was successful, you should be seeing messages appear on the terminal window as shown in the figures below. After programming the AD7193, the program will display the values of all internal registers. After that, it will go through 5 Demo Modes. | ||
+ | |||
+ | {{: | ||
+ | |||
+ | **Read Voltage Values referenced to AINCOM, UNIPOLAR Mode.** | ||
+ | |||
+ | {{: | ||
+ | |||
+ | **Read Voltage Values referenced to AINCOM, BIPOLAR Mode.** | ||
+ | |||
+ | {{: | ||
+ | |||
+ | **Read Differential Voltage Values, UNIPOLAR Mode.** | ||
+ | |||
+ | {{: | ||
+ | |||
+ | **Read Differential Voltage Values, BIPOLAR Mode.** | ||
+ | |||
+ | {{: | ||
+ | |||
+ | **Read Die Temperature Value.** | ||
+ | |||
+ | {{: | ||
===== Using the reference design ===== | ===== Using the reference design ===== | ||
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==== Functional Description ==== | ==== Functional Description ==== | ||
- | The reference design is a custom | + | The reference design is a simple |
The hardware SPI access allows sending and receiving data from the AD7193, programming its internal registers in order to decide which channels should be converted corresponding to AINCOM or its own differential pair, what GAIN, sampling frequency, etc. | The hardware SPI access allows sending and receiving data from the AD7193, programming its internal registers in order to decide which channels should be converted corresponding to AINCOM or its own differential pair, what GAIN, sampling frequency, etc. | ||
- | <note important> | + | <WRAP round important |
- | * Connecting the Pmod-AD5 | + | * Connecting the PmodAD5 |
- | * UART must be set to 57600 baudrate. | + | * UART must be set to 115200 Baud Rate for the Avnet LX-9 Microboard and ZedBoard or 9600 Baud Rate for the Digilent Nexys™3 Board. |
- | * Reference voltage | + | * When using AVDD > DVDD (= 3.3V), JP1 on PmodAD5 must be removed. The range for AVDD is 3.0V ≤ AVDD ≤ 5.25V |
- | </note> | + | * If using Xilinx Software Development Kit integrated Console as a Hyperterminal clinet, please uncomment all the commented **getchar(); |
+ | </WRAP> | ||
+ | <WRAP round important 80%> | ||
+ | When using the ZedBoard reference design in order to develop your own software, please make sure that the following options are set in " | ||
+ | |||
+ | <code c> | ||
+ | // Select between PS7 or AXI Interface | ||
+ | #define USE_PS7 1 | ||
+ | // SPI used in the design | ||
+ | #define USE_SPI 1 | ||
+ | // I2C used in the design | ||
+ | #define USE_I2C 0 | ||
+ | // Timer (+interrupts) used in the design | ||
+ | #define USE_TIMER 0 | ||
+ | // External interrupts used in the design | ||
+ | #define USE_EXTERNAL | ||
+ | // GPIO used in the design | ||
+ | #define USE_GPIO | ||
+ | </ | ||
+ | |||
+ | </ | ||
===== Downloads ===== | ===== Downloads ===== | ||
- | {{: | ||
+ | <WRAP round download 80%> | ||
+ | \\ | ||
+ | **Avnet LX-9 MicroBoard: **\\ | ||
+ | * {{: | ||
+ | |||
+ | **Digilent Nexys™3: | ||
+ | * {{: | ||
+ | |||
+ | **Avnet ZedBoard: | ||
+ | * [[https:// | ||
+ | * [[https:// | ||
+ | * [[https:// | ||
+ | * [[https:// | ||
+ | | ||
+ | </ | ||
===== More information ===== | ===== More information ===== | ||
* [[ez> | * [[ez> | ||
+ | * Example questions: {{rss> |