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resources:fpga:xilinx:pmod:ad7091r [10 Dec 2012 15:52] – Download Wrapper Alexandru.Tofanresources:fpga:xilinx:pmod:ad7091r [22 Feb 2013 12:15] – Text and archive Alexandru.Tofan
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 ==== Running Demo (SDK) Program ==== ==== Running Demo (SDK) Program ====
  
-<note tip>If you are not familiar with LX9 and/or Xilix tools, please visit\\ [[http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm]] for details.\\+<WRAP round tip 80%>If you are not familiar with LX9 and/or Xilix tools, please visit\\ [[http://www.xilinx.com/products/boards-and-kits/AES-S6MB-LX9.htm]] for details.\\
 If you are not familiar with Nexys™3 and/or Xilix tools, please visit\\ [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3]] for details. If you are not familiar with Nexys™3 and/or Xilix tools, please visit\\ [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,897&Prod=NEXYS3]] for details.
-</note>+</WRAP>
 Extract the project from the archive file (AD7091R_<board_name>.zip) to the location you desire.  Extract the project from the archive file (AD7091R_<board_name>.zip) to the location you desire. 
  
 ==== Avnet LX9 MicroBoard Setup ==== ==== Avnet LX9 MicroBoard Setup ====
  
-To begin, connect the PmodAD6 to J5 connector of LX9 board, pins 1 to 6 (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board.+To begin, connect the PmodAD6 to J5 connector of LX9 board, pins 1 to 6 (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board. Connect the USB cable from the PC to the USB-UART female connector of the board for the UART terminal. The board will be programmed through its USB male connector.
  
 {{:resources:fpga:xilinx:pmod:pmodad6.jpg?200|PmodAD6 and LX-9}} {{:resources:fpga:xilinx:pmod:pmodad6.jpg?200|PmodAD6 and LX-9}}
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 ==== Digilent Nexys™3 Spartan-6 FPGA Board ==== ==== Digilent Nexys™3 Spartan-6 FPGA Board ====
  
-To begin, connect the PmodAD6 to JA connector of Nexys™3 board, pins JA1 to JA6 (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board.+To begin, connect the PmodAD6 to JA connector of Nexys™3 board, pins JA1 to JA6 (see image below). You can use an extension cable for ease of use. Connect the USB cables from the PC to the board, one for programming (Digilent USB device) and one for the UART terminal (FT232R USB UART).
  
 {{:resources:fpga:xilinx:pmod:pmodad6_nexys3.jpg?200|PmodAD6 and Nexys™3}} {{:resources:fpga:xilinx:pmod:pmodad6_nexys3.jpg?200|PmodAD6 and Nexys™3}}
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 {{:resources:fpga:xilinx:pmod:PmodAD5impact.jpg?200|Programming FPGA in IMPACT}} {{:resources:fpga:xilinx:pmod:PmodAD5impact.jpg?200|Programming FPGA in IMPACT}}
  
-If programming was successful, you should be seeing messages appear on the terminal window as shown in the figures below. After programming the AD7091R, the program will display the value of the input voltage. Pressing [Enter] will perform another conversion and display the result.+If programming was successful, you should be seeing messages appear on the terminal window as shown in the figures below. After programming the AD7091R, you will be asked you to set the value of VREF. 
  
-{{:resources:fpga:xilinx:pmod:pmodad6demo1.jpg?600|UART messeges}}+{{:resources:fpga:xilinx:pmod:pmodad6_menu1.jpg?600|UART messeges}} 
 + 
 +If you use the default VREF(=2.5V) then just press [Enter] and the program will display the value of the input voltage. Pressing any key will perform another conversion and display the result. 
 + 
 +{{:resources:fpga:xilinx:pmod:pmodad6_menu2.jpg?600|UART messeges}} 
 + 
 +Here you are some of the errors that can appear while trying to introduce a wrong value for VREF. 
 +If any value besides 1 to 9 is entered, an error message will be displayed. If a value higher than 5250 or lower than 2700 is entered, an error message will be displayed. If entering less than 4 characters, please press [Enter] in order to validate your input. If 4 characters are entered, the result is automatically validated. 
 + 
 +{{:resources:fpga:xilinx:pmod:pmodad6_menu3.jpg?600|UART messeges}}
  
 ===== Using the reference design ===== ===== Using the reference design =====
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 The hardware SPI access allows receiving data from the AD7091R. The hardware SPI access allows receiving data from the AD7091R.
  
-<note important>+<WRAP round important 80%>
   * Connecting the PmodAD6 to the boards using an extension cable provides ease of use.   * Connecting the PmodAD6 to the boards using an extension cable provides ease of use.
   * UART must be set to 115200 Baud Rate for the Avnet LX-9 Microboard or 9600 Baud Rate for the Digilent Nexys™3 Board.   * UART must be set to 115200 Baud Rate for the Avnet LX-9 Microboard or 9600 Baud Rate for the Digilent Nexys™3 Board.
-  * Reference voltage is 2.5V +  * When using AVDD > DVDD (= 3.3V), JP1 on PmodAD6 must be removed and the external AVDD signal must be connected to J2 Pin 1. The range for AVDD is 2.7V ≤ AVDD ≤ 5.25V. 
-</note>+When using external VREF, connect the VREF signal to J2 Pin 3. The range for external VREF is 2.7V ≤ VREF ≤ AVDD. 
 + 
 +</WRAP>
  
  
 ===== Downloads ===== ===== Downloads =====
-<WRAP round download 50%>+<WRAP round download 80%>
 {{:resources:fpga:xilinx:pmod:ad7091r_lx9.zip|Reference design source code for Avnet LX9 MicroBoard.}} \\ {{:resources:fpga:xilinx:pmod:ad7091r_lx9.zip|Reference design source code for Avnet LX9 MicroBoard.}} \\
 {{:resources:fpga:xilinx:pmod:ad7091r_nexys3.zip|Reference design source code for Digilent Nexys™3 Spartan-6 FPGA Board.}} \\ {{:resources:fpga:xilinx:pmod:ad7091r_nexys3.zip|Reference design source code for Digilent Nexys™3 Spartan-6 FPGA Board.}} \\
resources/fpga/xilinx/pmod/ad7091r.txt · Last modified: 09 Jan 2021 00:49 by Robin Getz

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